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Original question:

BQ27421-G1: bq27421-G1 / Supply current is increased when SDA/SCL pulled Low

BQ27421-G1: Sleep current when external power rail is used for SCL/SDA pull-up resistor

Eran Dahan
Prodigy 70 points
Part Number: BQ27421-G1
Other Parts Discussed in Thread: BQ27421EVM-G1B

Hi,

I have facing the same problem too. 

This problem impacts the sleep current which should be according to spec <21uA but the actual is ~45uA. 

I have the same connection as . I have used your EVK with external power rail for pull up resistor of 3V.

The voltage of 3V is used because my host microcontroller has the same power rail (in my custom PCB)

Can you explain why sleep current is more than the spec current when external power is apply for SCL/SDA pull-up?

Thanks,

Eran

  • 0
    TI__Mastermind 19195 points

    Hi Eran,

    Typical value for sleep current is 21uA. The max is not specified.

    Best regards,

  • 0 in reply to Nick Brylski
    Prodigy 70 points

    Hi Nick,

    I always talked about average value and not the max value.

    Attached is photo from the current consumption (and excel sheet) of battery. All the measurements done on the EVK BQ27421EVM-G1B.

    I will describe my rationale:

    Setup:

    Point number #1 is when external voltage (3V) is apply for pull-up resistor [which is equivalent to my system power on].

    Point number #2 is when external voltage (3V) is down for pull-up resistor [which is equivalent to my system power off].

    As you can see, when the pull-up voltage is on and then off, the average current value (48uA) for sleep is not as specified in the data sheet – double the sleep current from the beginning (24uA).

    Also, as you can see, the current pattern is different when shot down is done for external voltage. It seems something wrong with the chip behavior in this scenario. I also found that this pattern is received for at least two different users at the same scenario.

    Please advice why we get different average value for current consumption from what is specified in the data sheet.

    Thanks,

    Eran

    FG.csv

  • 0 in reply to Eran Dahan
    TI__Mastermind 19195 points

    Hi Eran,

    We are looking into this.

    Best regards,

  • 0 in reply to Eran Dahan
    TI__Mastermind 34775 points

    Hello Eran,

    There seems to be a leakage path. Is your PACK voltage and Ext voltage 3V or they are different voltages from different power sources? I would recommend when using external voltage for pull-up jumpers to remove J2, then J8 amd then J9 to see where the leakage occurs. As Nick mentioned the datasheet has a typical spec, since other application factors can impact the sleep current. 

    I do see your baseline current shift up and down when the external voltage is applied. I would also recommend trying to lower the voltage to 1.8V to see if the sleep current drops down from 48uA.

  • 0 in reply to Damian Lewis
    Prodigy 70 points

    Hello Damian,

    The pack voltage (4V) and the Ext pull-up voltage (3V) are from different power source.

    The leakage current also occurred when Ext voltage pull-up is 1.8V or even if it is the same as pack voltage (4V) from different power source. 

    Note that when the Ext. voltage is connected to VDD of the Chip - no leakage has occurred and the sleep current stay at the same base line after ruining the same scenario. It seems to me that no matter what is the Ext voltage is, when it is not the VDD of the chip, the leakage always occur. 

    Regarding the jumpers, there is no affect if they are placed or not on the EVK. 

    In my application the Ext voltage is my host microcontroller voltage rail, so connecting the Ext voltage to VDD in my custom board is not possible.

    If there are other application factors that can impact the sleep current - why they are not specified in the data sheet? by the way, this factor of Ext voltage can be common in many applications. How do as users should be refer to typical value? 

  • 0 in reply to Eran Dahan
    TI__Mastermind 34775 points

    Hi Eran,

    I get your concern, but we can't test for every possible application use case imaginable. What we have done is give a baseline in the datasheet, which now you are working towards in your application. My next suggestion is to use a single supply and configure the EVM to use VDD instead of external voltage. There seems to be some interaction between your external voltage source and VDD causing this extra leakage current. I wouldn't recommend connecting external voltage to drive VDD, since its max is 2V. Check your setup for ground loop. Try shorting the grounds of your two power supplies together. Make sure both supplies have earth ground connections. If they don't then disconnect the earth ground of the one that has.

    I would verify this myself but I don't have an EVM and it will take me sometime to get one. I hope this helps. 

  • 0 in reply to Damian Lewis
    Mastermind 8040 points

    Damian Lewis said:
    we can't test for every possible application use case imaginable. [..] My next suggestion is to use a single supply and configure the EVM to use VDD instead of external voltage

    This is not a very reasonable answer, since the communication lines (SDA, SCL, GPOUT if used) will in almost any application be required to be pulled up to a processor's I/O supply, which cannot be the bq27421's VDD since this is explicitly forbidden by its datasheet ("This pin is not intended to provide power to other devices in the system.")