TPS650864: About power-up sequence of "TPS6508641"

user1466323

Part Number: TPS650864
Other Parts Discussed in Thread: TPS544B25

Hi,

I'm developping a original PCB which Zynq UltraScale+ MPSoC (XCZU3EG-1SBVA484I) is mounted.
I also adopt PMU(TPS6508641) for Zynq UltraScale+. Is the chip I choose correct?

I refer to a datasheet of TPS6508641.
When it was connected as shown in the figure6-9, I think they couldn't satisfy with the power-up sequence of Zynq UltraScale+ between“VCC_PSPLL”and“VCCO_PSIO".
Please look at figure below.
I've checked the power up sequence from DS925(xilinx datasheet).
Is my understand correct?

Thanks.

over 4 years ago

0 Kevin LaRosa over 4 years ago

TI__Genius 17380 points

Hello,

My understanding is that the critical part of sequencing is that VCCO_PSIO should not be powered up before VCC_PSAUX and that powering them up at the same time does not lead to leakage current.

The Xilinx designed Ultra96 board has them shorted together: www.96boards.org/.../ultra96-schematics.pdf

0 user1466323 over 4 years ago in reply to Kevin LaRosa

Prodigy 40 points

Hello,

Thank you for your quick reply!

Could you answer the following additional questions.

Q1.
In ULTRA96 as follows, TPS22920YZPRB(U31, U32) are used to generate "VCC_PSINTFP" and "VCCINT" These device have relation to “power up/down sequence”?

www.96boards.org/.../ultra96-schematics.pdf

Q2.
The filter in the datasheet, how can I compose it? Can I make it as ULTRA96?

Q3.
In ULTRA96, power supplies are generate by TPS6508641 only.
When I refer to the following page, VCCINT is generated by TPS544B25. Is this matter of the current capacity or something?

e2e.ti.com/.../843624
(SCHEMATIC_PMIC_MPSOC_XCZU6CG.pdf)

Thanks.

0 Kevin LaRosa over 4 years ago in reply to user1466323

TI__Genius 17380 points

Hello,

For Q1, it depends what architecture you want to use regarding PS/PL. I'm referencing the Xilinx power architectures outlined on page 34 of this document: www.xilinx.com/.../ug583-ultrascale-pcb-design.pdf

For Q2, I would recommend following Xilinx's example.

For Q3, yes, it depends on the configuration from Q1 mostly. If VCCBRAM = VCCINT then they can merge. If VCCINT = 0.72V then they need to be separate.

Power management

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TPS650864: About power-up sequence of "TPS6508641"