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TPS53681: DPS concerns for regulating performance

Yi Dou
Intellectual 545 points
Part Number: TPS53681

Hi E2E,

About DPS I have serval questions to consult:

1. With DPS and USR enabled,  extra phases will suddenly add into loop, the interleaving order and number will suddenly change, any risk of: refreshed current sharing→ phase current inrush→ output voltage variation here?

And what is the typical delay time between USR triggered and more phase actived? Internal comparator delay+ blanking time between phases?

2. At load goes up, USR makes all phases in operation, but in new steady state, the running phase number may decrease to desired, due to present output current level.(it is the same if load goes down)

When phase drops in these two conditions, I know there's delay between dropping phases one by one, but @dropping timing, the same issue happens, interleaving order and number will suddenly change, any risk of phase current inrush/output voltage variation here, as what I already claimed in no.1?

 

  • 0
    TI__Genius 11095 points

    Hello, 

    1- USR actually helps the transient current sharing. If USR is off, the sum current would need to build to the next phase adding threshold with the other phases off. With USR, it is added immediately, so the next pulses (you labeled Nph) get distributed instead of firing to one or fewer phases. 

    This has a similar benefit of reducing the output undershoot during a load step. Basically every design I know of which uses phase shedding, also has USR enabled. 

    Once USR is triggered, the higher ordered phases still require a blanking time to fire (this is an NVM setting, typically about 70ns). But this delay also applies between every phase. So, for example, if 1 phase is active, and USR adds 5 phases... (assuming the loop is saturated and firing pulses as quickly as possible)... PWM2 fires 70ns after PWM1, PWM3 fires 70ns after PWM2, etc.. Eventually the loop will not demand pulses at maximum frequency anymore, and the pulse frequency will be controlled by the control loop, which settles back to steady state when the output voltage is back at the regulation point. 

    2- Phases drop one after another with appx 85us delay each. Phase 5 drops 85us after phase 6, phase 4 drops 85us after phase 5, etc... 

  • 0 in reply to Matt Schurmann
    Intellectual 545 points

    Thanks, as you told that phase drop delay appx 85us fixed, any special considerations?

    Does 85us include output current detection delay? For example, controller needs to wait for telemetry circuits sensing time(because register value is used, it should be digital detection in my understanding) to tell DPS threshold is achieved, and then wait for a designed latency, the highest phase will drop.

  • 0 in reply to Yi Dou
    TI__Genius 11095 points

    The drop delay is just to serve as a de-glitch and keep phases active in case another transient occurs quickly. There is no special consideration about why this number is 85us, vs. 50us, or 150us. 

  • 0 in reply to Matt Schurmann
    Intellectual 545 points

    Another big concern for DPS, is about light load in DCM. For example, DPS enabled with 1ph operation only, according to DCAP+ principle in datasheet, when DCM is enabled @ both controller & Drmos side, the waveform should be like above.

    When load is reaching to 0, because on-time is fixed, switching frequency will decrease below 20kHz, generating acoustic noise. What's more, ripple and stability of PWM seems also bad. If ramp goes into saturation @CLK_ON, the results will be even worse.

    From datasheet, I didn't see any related actions TPS53681 can take, to handle in this condition. Could I take into consideration that DCM regulation of TI multiphase cannot respond well for this application?

  • 0 in reply to Yi Dou
    TI__Genius 11095 points

    This is essentially correct. TPS53681 does not have any mechanism which limits the minimum frequency, and it can be very low during light load operation in DCM.