Other Parts Discussed in Thread: TPS54528
Hello Guys,
In relation to the previous thread, the customer just got his prototype boards and have a very detailed follow-up inquiries. See below, customer follow-up inquiries in verbatim.
1. Power supply rise/fall
Please find attached the measurements. I compared two power switches. For Trise, the difference probably comes from the current limitation tolerance on both switch. For Tfall, the results are better with MIC2007 because its discharging resistance is lower (125 Ohms typ) than AP22653 (600 Ohms), but the AP22653 cost is much lower :) First we see the voltage dropping quickly (self residual consumption by the drivers), and then the voltage drops at a lower rate because it is only capacitor discharge (total 4µF approx.) that occurs. Be careful on the timebase, it is 200µs/div for both Tr measurements, but 500µs/div pour MIC2007 Tf measurement and 2ms/div for AP22653 Tf. These measurements have been done on just one board for each power switch, so we can expect the power up rate to be 1.5 times faster in the worst case (300µs for 0V to 3V levels) with current limitation tolerance. Can you tell me how you feel about the power up speed, is it ok (not to fast) ?
2. Power supply undershoot
I made measurements on VCC on driver pins at display on/off transcients (full power), nominal VCC level is 3.15V, and I notice an undershoot down to 2.95V during 5µs when display is being enabled (TPS54528 converter loadstep response from 0 to 5A). Even if below the nominal 3.0V minimum level, can I consider this is ok ?
3. Input logic and chronogramms
I'm analysing bus timings and waveforms, and the implementation of clock in your device makes things a little bit harder (sample SIN on CLK rise with 3ns hold time, and SOUT update 8ns after same CLK edge) because I did not ancitipated that. My fear is that my CLK Tr may be too slow, I may have a problem if device N have a low rising threshold and device N+1 a much higher threshold, the SOUT of chip N may be updated before or during the sampling period of chip N+1.
In my case there is a non negligible length between MCU and last driver (12 inches of trace) and 16 drivers share the same CLK. In my previous design I use a serial 100R resistor, but the Tr is high and the issue I described just before may occur in some cases (I did not observed it on my board that works, but I cannot extrapolate 16 drivers tested to 300K drivers/year...). I tried to have a very low Tr using a driver buffer, I have either an overshoot on last drivers (I can reduce it with a small serial resistor), but also a reflexion seems to occurs on trace, and I have a small folding in the signal rise on the drivers near the MCU.
I don't want to have EMC problems so I'm intending to restore the 100R resistor on CLK (and other signals too). In order to delay the SOUT signal update incoming to the SIN of next driver, I will add a resistor between SOUT-SIN link of each driver pair (probably 2.5K I already use in the design). This will increase the rise time and add an approx. 100ns delay on the SOUT transition seen on next driver and ensure I don't have asynchronicity.
BUT this solution can only work if driver input SIN and CLK gates are all in schmitt trigger configuration to avoid unstable transition between Vil/Vih due to long rise/fall times. Datasheet indicates SCLK input is schmitt trigger, no mention done on other inputs. But the internal diagram shows that each input uses schmitt trigger. What have I to consider ?
Thanks a lot!
Art
