LM5116: Output glitch after inhibiting LM5116 controlled buck

Quinn Kneller

Part Number: LM5116

Hi,

I am using the UVLO pin on the LM5116 to enable/inhibit a buck converter. If I inhibit the converter at full load I see a pulse on the output, typically up to a quarter of the nominal output voltage, a few ms after the output initially fell to zero. If I reduce the load the output inhibits cleanly.

As far as I can see, I still get activity on HO despite ULVO being below 1V at the time of shutdown

What are TI's suggestions for a fix or workaround? My inhibit signal is opto-isolated so is too slow to drive EN directly.

over 4 years ago

0 Timothy Hegarty over 4 years ago

TI__Guru 74012 points

Hi Quinn,

Is the UVLO voltage falling smoothly near the threshold? Please send the schematic and waveforms of UVLO and VOUT.

Regards,

Tim

0 Quinn Kneller over 4 years ago in reply to Timothy Hegarty

Prodigy 140 points

Hi Tim,

Thank you for your quick reply. I can't post schematics on a public forum, but I have some waveforms I can share.

UVLO has decayed well past the threshold when the LM5116 kicks back into life:

I have also looked at what is happening to the Soft-Start pin during this to see if that provides some clue as to what is happening;

Generally, if my load is high enough for Vout to decay to zero before SS has reached zero, I see the glitch on Vout. If I reduce the load so it decays slower than SS then I don't see the glitch.

Quinn Kneller

0 Timothy Hegarty over 4 years ago in reply to Quinn Kneller

TI__Guru 74012 points

Hi Quinn,

Thanks for the waveforms. I will review the UVLO behavior. In the meantime, try using the EN pin to disable the controller.

Regards,

Tim

0 Quinn Kneller over 4 years ago in reply to Timothy Hegarty

Prodigy 140 points

Thank you for looking into this.

Our first pcb revision had the inhibit/enable wired up to EN but unfortunately that caused other issues as we simply couldn't drive it fast enough. So when you know why UVLO isn't working as expected, please come back to me.

Quinn

0 Quinn Kneller over 4 years ago in reply to Timothy Hegarty

Prodigy 140 points

see below

0 Timothy Hegarty over 4 years ago in reply to Quinn Kneller

TI__Guru 74012 points

Hi Quinn,

Please check that current limit is not engaging during the shutdown (note that UVLO controls the hiccup interval, set by the cap on UVLO).

Regards,

Tim

0 Quinn Kneller over 4 years ago in reply to Timothy Hegarty

Prodigy 140 points

Hi Tim,

Thank you for your reply.

Current limit shouldn't be engaging - the buck stops switching during shutdown (until just before the glitch appears). Though I can see how Vout dropping would increase the re-constructed current signal if it was switching. Unfortunately the LM5116 doesn't bring the current amplifier signal out.

Any thoughts on which other signals might help establish what is happening?

Quinn

0 Timothy Hegarty over 4 years ago in reply to Quinn Kneller

TI__Guru 74012 points

Hi Quinn,

I'm looking into this behavior and will get back to you shortly. In the meantime, try disabling using EN.

Regards,

Tim

0 Quinn Kneller over 4 years ago in reply to Timothy Hegarty

Prodigy 140 points

Hi Tim,

Thank you for your reply and I look forward to hearing more about the UVLO behavior.

As noted above, we tried disabling using EN, but that didn't work correctly either. In our case we ended up with spurious HS drive pulses, causing a glitch during start-up.

Quinn

0 Timothy Hegarty over 4 years ago in reply to Quinn Kneller

TI__Guru 74012 points

Quinn,

Use a sharp edge EN signal.

Regards,

Tim

0 Quinn Kneller over 4 years ago in reply to Timothy Hegarty

Prodigy 140 points

Tim,

Thank you for you suggestions.

When do you think you will have an answer on why UVLO isn't shutting the supply down as specified in your datasheet?

Quinn

0 Timothy Hegarty over 4 years ago in reply to Quinn Kneller

TI__Guru 74012 points

Hi Quinn,

Here is the explanation of the shutdown waveforms:

As VOUT is coming down, SS is following FB. The FB voltage (gold waveform), a scaled version of VOUT, gets pulled to GND below SS (blue waveform). When FB < SS, COMP will begin to increase and initiate switching until SS reaches 0 V. This aligns with the case when VOUT (and thus FB) is slower than SS such that the issue doesn't occur.

Note that the controller should in in STANDBY state when the UVLO voltage is less than 1.225V. Please check the measurement of the UVLO voltage.

Regards,

Tim

0 Quinn Kneller over 4 years ago in reply to Timothy Hegarty

Prodigy 140 points

Hi Tim,

Thank you for that explanation, that ties up pretty well with what I thought might be happening and I have some control on how FB is driven, so can do something about that.

UVLO is definitely below 1.2V, but I suspect that the main mechanism used by UVLO to put the controller in Standby is by discharging SS to zero.

Quinn

0 Timothy Hegarty over 4 years ago in reply to Quinn Kneller

TI__Guru 74012 points

Quinn,

Thanks for the update. Yes, SS should be low and you can pull that down externally if needed.

Regards,

Tim

Power management

Power management forum

LM5116: Output glitch after inhibiting LM5116 controlled buck