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Advice for 200W design

Tak
Intellectual 480 points
Part Number: UCC28780
Other Parts Discussed in Thread: TL431, LM317

Dear Ulrich

I designed the power supply with the following specifications with UCC28780.

AC85V～AC276V

Pout=200W(Vout=32V,Iout=6.5A)

Fsw(min)=200kHz

Transformer Np:Naux:Ns=14T:4T:3T , Lpri=23uH(@100kHz) ,Ll=2.5uH(@100kHz)

So far the prototype is working.
However, I think it is necessary to modify it for more stable operation and higher efficiency.

Since I attached the circuit diagram, could you confirm that there is no problem with the design value?

I am particularly concerned about feedback and clamp .

Let me ask you a few questions.
① About Cclamp

I have confirmed the best from the datasheet and excel tool. As a result, we have implemented the equivalent of 0.66uF.

(However, I think the effective capacity is 0.3-0.4uF.)

Unfortunately, when I try to extract 150W or more with this design value, Fsw drops to about 50kHz and causes abnormal operation.
However, when I changed the Cclamp to 0.1uF (effectively 0.05 to 0.06uF), I was able to output up to 200W without any problems. Fsw also keeps over 200kHz.
Do you have any opinion on the cause and the optimum number for Cclamp?

I simulated it with SIMPLIS, but I think that 0.1uF or less is more stable.
What do you think? Also, do you know the cause of the abnormal operation?

②About the capacity on the secondary side (with active clamp)

I set Co1 to 4uF and Co2 to 1140uF as initial design values. From the data sheet, we decided that Co1 should not be too large.
However, the evaluation board circuit diagram you provide has a relatively large Co1. For example, 66uF.

How much capacity is best?
However, in my case, the voltage on the secondary side is 32V, so a rated voltage of 35V or higher is required.

This class of ceramic capacitor is very expensive. Can a hybrid capacitor be used instead? I think the ESR will increase a little. But it's inexpensive.

③Vddについて

Since it was found that the rated voltage of the MOSFET and gate driver was exceeded, TPS7B4250 was mounted with reference to the evaluation board.
Initially I implemented LM317DCYR, but it fails to start. I think this is because the starting current exceeds the protection threshold. Is the idea correct?

④About the peak current generated when switching from ABM to AAM

A very large peak current flows when the operation mode changes. I am concerned because the actual measurement is considerably larger than the SIMPLIS simulation.
In particular, if Ccs is set to 22pF or higher, the transformer primary current will exceed 10A. Currently, Ccs is set to 2.2pF.
As a result, the peak current has dropped considerably, but I'm not sure if this is reasonable.
Do you have any advice?


There is one point to declare.
I have created a ground plane directly under the RDM, RTZ, SWS and BUR pins.
Since it is an analog IC, I thought it needed a large plain ground.

However, after the trial, I noticed that the data sheet says to avoid the plain ground.

This pattern layout may also be bad. Of course, we will fix it in the next trial.

B.R. Tak

8203.shematic.pdf

  • 0
    TI__Prodigy 590 points

    Hello,

    Currently Ulrich is not being assigned threads on E2E (he should be back in January). I have assigned your thread to the person taking over in the meantime.

  • 0 in reply to Pye Naing
    TI__Expert 7080 points

    Hi Tak,

    There are so many questions in this post, each of question can be a topic for ACF topology. I'll try to briefly reply to you in below:

    1. About Cclamp . You should attach some abnormal waveforms that the power stage running at 50kHz and 150W load.  the waveform should at least include  Primary low side VDS , Transformer Primary winding current. Basically , Cclamp should not influence the switching frequency . and based my experience , large Cclamp capacitor will give you a more stable operation at ABM mode. In TI excel calculation tool table "Secondary Resonance and ARC"  Item B "C01 Adjustment" design guideline , there are two waveforms show how to adjust the resonance capacitance. although at secondary side resonance , C01 is dominant for the resonance capacitor , but Cclamp will impact the energy storage and transfer. the capacitance value on our EVM board still a good start point for your design. you can adjust them based on the waveform you captured on your board.

    2. About the capacity on the secondary side (with active clamp)  see above reply.

    3. Vdd ??  , your idea is correct , the start up current controlled by UCC28780 can be calculated by Depletion mode start up Mosfet Vgs threshold voltage divide the resistor which in series at SWS pin plus controller internal 1k resistor . so roughly the  start up current ~= 2V/(1K+470ohm) =1.36mA , If the load on VDD pin exceed this value , the VDD cap will not be pumped to turn on threshold.

    4. About the peak current generated when switching from ABM to AAM.

    Can you show some waveforms to let us know what the peak current you seen when ABM transient to AAM ? Usually Ccs is set from 22pF to 100pF  , the purpose of this cap is to filter some noise caused by hard switching  to avoiding narrow pulse on PWML. also high capacitance in here also will lead to turn off delay of the mosfet . that will cause higher OPP level.  if you applied a 2.2pF cap on CS pin , make sure the peak current dropped was not caused by leading edge blanking turn off.

    5. We are not recommend to create a ground plane under RDM, RTZ specially under VS pin trace and it's divider resistors . since it will impact controller's operation , please correct it at next time PCB layout design.

    Some other comments about your design :

    6. Transformer Lm is 23uH  Lk is 2.5uH , looks like Lk is large  2.5/23= 10.8% , high leakage inductance will sacrifice the efficiency.

    7. For silicon Mosfet design , Fsw_min =200Khz is a little higher . 140kHZ maybe a more reasonable Fsw for efficiency.

    Hope above comments can help you.

    Thanks.

  • 0 in reply to Jaden Ning
    Intellectual 480 points

    Dear Jaden

    Thank you for the meaningful answers !

    First I lower the Lk of the transformer. I also redesign Fsw (min) to 140kHz. Also, in the next prototype, the plain ground will be deleted.

    Thank you for advise!

    Is the design value of the circuit diagram I sent correct?

    How much does Co1 advance?

    Do you think the design value for negative feedback near TL431 is appropriate?

    The Vdd power supply is suitable for the method using TPS7B4250 as shown in the attached circuit diagram, isn't it? (LM317 was NG)

    I don't understand why it doesn't work stably unless the capacity of Cclamp is reduced. Attach the waveform.

    abnormal condition.pdf