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TPS7A8101: output delay

user6064774
Prodigy 170 points
Part Number: TPS7A8101

Hi：

I use TPS7A8101 for 3.3V to 1.2V. EN connect to VIN. But some product 1.2V output delay 30-50ms when EN is enabled while most product 1.2V output immediately when EN is enabled.  Below figure is my SCH and test result(red is EN and blue is 1.2V). So is this delay normal?  Why is this result？ Thank you.

  • 0
    TI__Genius 13085 points

    Hi,

    When you ask if the delay is normal I believe you are referring to the time period when the output voltage stays low and that is what I'll address, if that is not the concern please let me know. This delay is normal when an NR capacitor larger than 2.2nF is used, below is a description of why this happens and what can be done to eliminate it. 

    In the scope shot you can see a very slight increase in the output voltage but then it stays flat. This device has two modes of operation, high current mode and low current mode (this was done to improve/ensure stability at low currents) and this flat step at startup is caused by the transition from High Current mode to Low Current mode during Startup. As the LDO starts to charge Vout the device starts in High Current Mode and then transitions into Low Current Mode due to the large NR capacitor and this transition during startup causes the gate of the Pass FET to be pulled high which turns off the Pass FET until the gate can be pulled low enough to turn on the Pass FET and start the charge of Vout again.  

    How to reduce/eliminate the flat region at startup
    •Any NR cap value that extends startup time(from EN to 90% * Vout target)  to more than approximately 200us, will see flat step behavior
    •Cnr values larger than 2.2nF will extend the startup time enough to cause the flat region
    •To adjust length of time of the flat region, Cnr can be adjusted
    •Larger Cnr will result in longer flat region
    •To adjust the amplitude of flat region the Cout or load current can be adjusted
    •Larger Cout will result in smaller amplitude
    •50-200mV amplitude is expected for Cout of 1uF-50uF
    •Larger load current will result in smaller amplitude
    •Note that since the amplitude is very small resistive loads will need to be sized accordingly
  • 0 in reply to Kyle Van Renterghem
    Prodigy 170 points

    Hi ：

    Yes. The problem what I mentioned is output voltage staying low. I am surprised most of products is ok(delay is small) but some product output voltage delay more than 20ms. So I can not be sure all products will OK if I change Cnr to 10nf .Or I need to change it to 2.2nF ？I hope the delay is less than 5ms. Thanks.

  • 0 in reply to user6064774
    TI__Genius 13085 points

    Hi,

    Yes to eliminate the delay Cnr will need to be changed to 2.2nF or less.