[FAQ] UCC5310: How do I implement interlock protection using the UCC53XX family in half-bridge applications?

What is interlock protection, and how is it implemented in a driver?

IGBTs and Silicon/SiC MOSFETs are critical to the operation of the system in which they operate, so it is important that they are protected. The devices are not only crucial for efficient operation; they are also one of the most costly components in a system. When devices are arranged in a half bridge, as shown in Figure 23, they cannot both switch on at the same time. Thus, dead time is used before the switches change states and both devices are turned off momentarily during the switching cycle. If the devices turn on at the same time, shoot-through will occur and cause a large current spike and potential failure. Shoot-through can occur in the event of an incorrect dead-time calculation that is too short, varying propagation times between drivers, or noise at the input. Interlock is a feature in gate drivers to prevent shoot-through. Logic circuitry combines the positive and negative inputs of a gate driver such that they can never be on at the same time. Think of it as an integrated dead-time feature that takes delays inherent to the driver into account. Even if there is an error in the user-programmed dead time, the driver interlock will not allow both outputs to turn on, thus preventing damage to the half-bridge switches. Interlock can be implemented for single-output or dual-channel drivers, as shown in Figures 24 and 25. In a dual-channel driver, the input channels are tied together internally; in single-output drivers, the inputs are tied together externally.

Specifically for UCC53XX devices tagged in this post (all but UCC5304 which has a single-input and requires an external logic gate to implement interlock), here is a modification to an app note that discusses using the UCC53XX devices in a half-bridge. For example, I have modified Figure 5 to include the interlock functionality.  The high-side input is provided to IN+ of the high-side driver, as well as IN- of the low-side driver. Similarly, the low-side input is provided to the IN+ of the low-side driver, as well was IN- of the high-side driver. This, if there is an error condition in the controller which tries to drive IN+ of the high-side, and IN+ of the low-side drivers high at the same time, these new connections shown in red will prevent both drivers from turning on and causing cross-conduction, or shoot-thru of the half-bridge transistors. This will prevent them from becoming damaged during this logic error. Please see Tables 4 and 5 of the UCC53XX datasheet to understand the logic of the input terminals.

Please see this excellent document for more information on  IGBT & SiC Gate Driver Fundamentals. Interlock is discussed on page 18.

For clarity, the RC filters suggested on the inputs are not shown in this diagram. They should still be placed on your PCB to help with noise mitigation. They help prevent false pulses from getting thru to the output due to noise between the grounds.

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Best regards,

Don