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UCC28951: Frequency Dithering (to ease conducted EMI)

Part Number: UCC28951

Former Case No.: CS0379890

I am considering modulating the switching frequency of the UCC28951 to ease meeting conducted EMI requirements. In this application the frequency range being considered is 21...30kHz and the vary rate is 0.846...1.134kHz/ms.

Are there any inherent issues doing this with this controller?

If I understood the operation of the Oscillator block (on page 18 of the datasheet) in Master mode (I'd guess RT drives a current mirror to drive a cap and provide the 0.8...2.8V RAMP signal) I could easily 'tweak' the current into the RT pin to generate the dither.  If my guess is oversimplified I could pull-down RT and drive a 2x 50% duty square wave into the SYNC pin.  The latter would not be my preference, but...

Perhaps you already have considered this for this (or another similar) controller and can provide a circuit recommendation?

Let me know,
Jeff

  • Hello,

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  • Hello,

    The UCC28951 uses ZVS which should reduce it's EMI signature greatly to reduce EMI.

    We aware of the frequency dithering technique to reduce EMI and it is recommended the operating frequency not be varied more than +/- 10% so the PWM converter and magnetics will function correctly.

    A lot of customers have reported having the best luck dithering the frequency at 10 to 20 kHz, with a 10 kHz rate.  This is generally done with 100 kHz designs and would not be affective with a 30 kHz design.

    The following link will bring you to application note that can be used to dither the frequency of PWM controller.  We have not tried this circuitry with the UCC28951, however, we can not see any reason why it would not work.

    Regareds.

  • Thank you for your input.  The magnetics design will be capable of running indefinitely at 20kHz.  The first question is if the internal loops are affected by the oscillator frequency (it doesn't appear so in the block diagram).  The second question is how the internal oscillator functions.  Figure 2 of the attached PDF implies a current mirror.  The UCC28951 uses the external reference and a resistor to the RT pin.  Perhaps it uses a comparator circuit to determine master/slave status?

    Can I get a simplified diagram or explanation of the UCC28951 oscillator so I can appropriately design the dither circuit?  This is something I need to do now and have reviewed prior to being able to 'play' with the actual hardware to see how it really works.  Thank you.

  • sorry... see my 2021/1/11 12:03 post...

  • Hello,

    The block diagram from the data sheet shows the ramp peak and valley charging between 2.8V and discharging down to 0.8V.  There will be an internal comparator that will charge the internal capacitor based on the current mirror until the ramp reaches 2.8V and the a comparator will  be triggered initiating a discharge of the oscillator ramp.  

    The oscillator circuitry design is proprietary and the functional block diagram of the oscillator in figure 19 is all we are allowed to give out.   The UCC28951 because it has zero voltage switching is generally not used with frequency dithering.  TI has not studied or written application notes on if and how well the UCC28951 will work with frequency dithering.  However, I believe it should work but you will have to figure out what the charge current is based on data sheet parameters.  The following equations should help you derive the equations that you need.

    dt = C/I*dV

    frequency = 1/dt

    In this low frequency design do you think frequency dithering is really needed?  Your fundamental frequency is going to be well below 150 kHz and with every octave of the fundamental the EMI noise generally drops by a factor of 2. 

    You will have some high frequency ringing on the secondary of the PSFB and in this low frequency design dithering will reduce average EMI with spread spectrum.  However, to reduce peak and quasi peak EMI I have heard the dither frequency and rate needs to be above 10 kHz to see any benefit.

    I am interested in how much your dither circuit reduces average, peak and quasi peak EMI in your low frequency design.  When your evaluation is done could you share your results with the e2e audiance?

    Regards,

  • Given the unique nature of the master/slave implementation I would assume the input of the current mirror is the base of an NPN transistor with its emitter connected to 2.5V.
        Is this what I can expect to see when driving current into the RT pin?

    Yes, my dithering is to address the harmonics at and above 150kHz.  Dithering ±10% around 25kHz means the harmonics are also dithering ±10%, so it would be the equivalent of a ±10kHz dither when operating at 100kHz.  Your comments about zero voltage switching makes the assumption this controller is being used in the "typical application".

    This is a high power design and the intent is to knock down the harmonic amplitudes enough to allow the use of a small and simple line filter.

    I too am restricted on what I can share, but I should be able to post general comments about the approach and results after prototype testing...

  • Hello,

    Current mirrors can be setup with NPN transistors and FETs.  It will be either one of these configurations.

    The equations in frequency in the data sheet are reference around 2.5 V, so I believe your correct.

    I have also used controllers for designs they were not intended for and that makes engineering interesting.  Good luck with your design and thank you for choosing Texas instruments.

    Regards,

  • I apparently won't get what I'm looking for, but your confirmation I am on the right track is helpful.  I'll just make sure I have enough hooks for my prototype to be able to do what should be necessary.  Thanks!