TI Friends & Family,
Our customer is currently designing an application using TPS65400 with these targets:
- SW1: 1.0V @ 2.6A
- SW2: 3.3V @ 3.0A
- SW3: 1.8V @ 1.8A
- SW4: 1.5V @ 1.8A
They are currently using the Arty_Z7_Sch.pdf (attached) as a reference, as it uses the FPGA that is currently being used for this application. The issue is with the compensation network values: Rc, Cc and Croll. Namely, cannot easily match the values used in the attached application, with either Webench or calculations using the TPS65400 data sheet. Specifically, if Co = 22uF (or equivalent derated value) used as on Sheet 12 of 13 of the schematic, they get Rc values that are far too low in comparison to what is being used in the application. But when they try to account for all the capacitance hanging off of the corresponding 1.0V, 3.3V, 1.8V and 1.5V rails, they get values that are far too large. What’s the proper way to account for the output capacitance in designing the compensation network?
For reference, here are the total capacitance values hanging off of each rail in my design:
- Total uF on +1.0V: 617uF
- 1x 22u
- 1x 330u
- 2x 100u
- 1x 47u
- 3x 4u7
- 8x 470n
- Total uF on +3.3V: 350 uF
- 1x 22u
- 1x 100u
- 4x 47u
- 7x 4u7
- 15x 470n
- Total uF on +1.8V: 227uF
- 1x 22u
- 1x 100u
- 2x 47u
- 2x 4u7
- 4x 470n
- Total uF on +1.5V: 148uF
- 1x 22u
- 1x 100u
- 1x 4u7
- 4x 470n
- 2x 10u
We look forward to hearing back.
TY,
CY
