TPS1HB08-Q1: How much time during overcurrent is needed for shutdown?

Hi Yoshiki, 

Once an overcurrent event has been detected, a fast trip response of 7us will take place before the device starts to regulate or shut off the output current. Let us know if you have any further questions. 

Hi Francisco, 

I understood that there is 7us between overcurrent event detection and shutting off output current .

How much deglitch time, when output current exceeds the current limit threshold, is needed to detect overcurrent event? I would like to know overcurrent detection sensitivity.

Regards,
Ochi

Hi Yoshiki, 

This is not a specified value, however,  you can typically expect 50us from the time the current limit occurs to the time it is reported on the SNS pin. 

Hi Francisco, 

Could you confirm me my whether understanding is correct or not? In addition, do you mean duration A (or OCP deglitch time) is not specified, is it correct?

Duration A: How much time is it required?

Duration B: Fast trip response 7us from OCP detected to output shut off

Duration B+C: SNS pin reported response 50us 

Regards,
Ochi

Above figure is for reference for my questions 

Hi Yoshiki, 

We are checking this internally and I will get back to you as soon as get an answer here. 

Hi Yoshiki, 

Current limit accuracy for the High Side Switches is different for instantaneous over-current events and slow current creeping events. When the current limit is detected instantaneously when the FET in the current mirror is saturated by a fast increment of load current. However, for slow current increase this FET will remain in the linear region affecting the current limit accuracy. The following application note, section 4.1 refers to this issue more in dept.

https://www.ti.com/lit/an/slva859b/slva859b.pdf

Hi team, 

Thank you for your supporting. 

I took a look at https://www.ti.com/lit/an/slva859b/slva859b.pdf which says that " It does not affect the lower on resistance TPSxHBxx devices due to differences between the device architectures." 
I understood that TPS1HB08-Q1 has no current limit accuracy problem @ slow current creeping events, is my understanding correct?

Again, Could you confirm me my whether understanding is correct or not? In addition, do you mean duration A (or OCP deglitch time) is not specified, is it correct?

Duration A: How much time is it required?

Duration B: Fast trip response 7us from OCP detected to output shut off

Duration B+C: SNS pin reported response 50us 

Reference to https://www.ti.com/lit/an/slva859b/slva859b.pdf
The current limiting accuracy for TPSxHxxx devices is different between instantaneous over-current events and slow current creeping events. Current creeping is defined as a fault that results in the slow increment of load current from a normal operating level to the set current limit. It does not affect the lower on resistance TPSxHBxx devices due to differences between the device architectures. Due to the electrical characteristics of the sense FET in the current mirroring circuitry of the affected devices, the ratio of the load current to the mirrored current is only defined while the FET is in its saturation region.

Regards,
Ochi