LP8867-Q1: LP8867-Q1: analog dimming and component recommendations

Hello,

I have another one question - due to topology of device digital control and power grund is interconnected in power supply of device, so it is not possible to connect digital and power ground in backlight driver. What grounding scheme use for this configuration ? Use power ground for powering boost and separate ground connected near backlight driver for analog part of backlight driver, with digital input signal referenced to power ground and not to "analog" ground?    

Also I have some aditional questions/details to questions

Ad 1.

I plan to entirely replace NTC circuit with fixed resistors as temperature protection of backlight is done in software, reason to use temperature input instead of direct driving ISET is that ISET have 60uA full scale current and this complicating selection of FET because of its leakage current in off state (mainly at higher temperatures). The TSET/TSENSE dividers works on several higher current so leakage in closed FET is negliegable.

Ad 2.

So there is need to use external reference if voltage is used for driving of analog dimming via TSET/TSENSE, otherwise supply change can get modulated to LED current (not much matter if is used for emegency dimming of backlit due to overtemperature, but matter if is used for normal regulation).

Ad 3.   

Thats good - no need to tight time synchronization between enable signal and PWM start.

Ad 4.

Current ripple and resulting votage ripple is not problem to calculate from input and output voltage range (and thus duty cycle) as it not much depends on IC itself. But this not help too much for selectioin of capacitors because I dont know which value cause instability of boost. My main concern is that ceramic caps working vith relative high voltage (in this case 26V typical, 27V maximal, 32V OVP trip) loose significant part part of capacity and loosing continue due to ageing. It is little tricky to characterise this effect on capacitors (datasheet usualy don't specify or guarantee this parameters and mearsuring means that I know samples that have been measured but not what is guranteed). So all numbers is some kind of estimate (less or more exact), way to workaround this is left enought headroom for worst case. That is reason for which I need to know where is borders of boost safe operation - it is not much problem to use bigger capacity (altought it takes more space on PCB and more cost) when designing device, problem will be if devices start to failing due to degraded capacitors or maybe due to too high capacity (in case that capacitors will be better than estimated).

So I appreciate any help with right capacitor selection.

Ad 5.

OK i will use 1nF decoupling. Have this slowing down of driver some relevant impact to maximal PWM ratio or it is negliegable ?

With best regards,

Pavel Patera

Hi Pavel,

You can refer to the schematic of EVM board under product folder on ti.com for using the separate ground.

1. When the MOS is off, the resistor is several Mohm compared with the typical ISET resistor value 20kohm. Therefore, the accuracy of ISET is also OK. However, you can also try with TSENSE. But it is hard to achieve NTC derating and current change at the same time.

4. Good question. For headroom voltage, the maximum output voltage is recommend to be 2V~3V higher than the maximum voltage of LED string. For the output capacitors selection, if you use ceramic capacitors, you need to considering the actual effective value @ maximum output voltage since there is DC derating. And for the electrolytic capacitor, you also need to consider the aging derating. So from the side of  loop stability views, it will typically get the minimum value of output effective capacitors through converter modeling or AC sweep simulation according to the requirements of system. This is a little bit complicated and usually is different for the different input and output conditions. You can provide your input and output conditions so that I can recommend a minimum effective value for you.

5. For dimming ratio, it is negliegable.

Hello,

from backlight datasheet:

There are two string 130mA each - so it is necessary to use two channels in paralel (each driving 65mA) for each string. Voltage for each string is in range 18V to 27V (in whole temperature range and including all tolerances), typical voltage should be about 21V@25 deg. C. Maximal forward voltage deviation between strings less than 2V.

boost input is from 12V (nominal) bus, permissible voltage range for bus is 9V to 15V (under 9V board main supply shutdown and cut power to control logic and over 15V board overvoltage protection trip).

Boost operation is planned in frequency range 3 with spread spectrum enabled - choosen Rfset=42,2kohm (approx 1390kHz). Recommended (from datasheet) L=10uH

For used output voltage feddback T-divider with 130k/10k/16k (Vmin=16,8V Vinit=28,9V Vmax=30,5V) with 68pF feedback capacitor (NP0 ceramic).

With best regards,

Pavel Patera

Hello,

thank you for your reply.

Is there any limit for maximal capacity in wiew of boost stability or it is just limited only by time required to charge such capacity to output voltage during boost state ?

With best regards,

Pavel Patera

Hi Pavel，

We don't have strict design consideration for maximum output capacitor. Bigger output capacitor will reduce the dynamic performance but increase the loop stability usually. The boost start time is around 50ms and should be charged to initial voltage during this period.