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UCC28742: Open feedback output drive issue

Jaikumar Munusamy1
Prodigy 20 points
Part Number: UCC28742

I’m currently working on a Flyback design & using UCC28742. I’m now testing for a particular condition called open feedback response.

Basically, this is a test where I would be checking the output overvoltage limits. System is running and I would be opening the feedback to the controller at runtime and measure the outputs. I’ve two outputs being 15V & 24V.

Supply voltage range is 0-450Vdc. 15V bus rating 1.5W, 24V bus rating 20W.  Based on my set resistors at Vs pin (60k4-top, 24k9- bottom), output is ON at inputs 92Vdc & OFF at 39Vdc.

While testing open fb, things were all ok until 66Vdc, but below this point and until 39Vdc, the output is starting to drive and I’m getting voltage on V15 bus as max as 25V (very little load 10mA - ~0.15W) and relatively high load on V24 bus (~10-20W).

Since I’ve a Zener on V24 (27V Zener), the voltage is limited to 30V max (I’m safe here). But power on V24 goes up to 30W in this condition(const resistance load).

 

From this there are two dangers,

  1. I can’t let 15V to jump >20V but this 25V
  2. Max power on SMPS I’ve designed is 22W, can’t let 30W on it which will eventually heat up the components on the bus.

 

Few questions:

  1. I would like to understand why this happens at first place
  2. Threshold on input voltage is 92-39 = 53Vdc. It seems to be high. Start is 210uA & stop is 75uA

Why input under voltage isn’t configurable?

  1. Or there any solution to this problem?

  • 0
    TI__Guru* 86266 points

    Hello,

    I would study the aux winding to see why OVP is not tripping.  It should trip when VS is greater than 4.6V when the aux voltage is high when the fly back converter is delivering energy.  The only time during this time that OVP will not reset is during TLK_RESET which blocks out the leading edge leakage spike.  The blanking time is explained on page 14 and figure 11 of the data sheet.

    Please note for your design to work correctly the on time needs to be greater than TLK_RESET.  Also the transformer's magnetizing inductance and turns ratio needs be set on max frequency and volt second balance.

    I have seen issues with transformer saturation causing issues with over voltage. You can verify this is not happening through volt second balance and studying the CS resistor signal. If the CS signal is a nice linear ramp than the transformer is not saturating.  If is curved it generally indicates the transformer is saturating.

    Also it is recommended that you have 1 to 2 mA of pre-load to prevent over voltage.  From your inquiry it seems that you have this, so this is not the issue.

    The device checks for an input under voltage when the FET is on the high side resistor on the VS pin sets the trip point for UVLO turn on.  Studying the aux voltage with an oscilloscope will help you determine if the FET should not be turning on.

    Regards,