• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 63 subscribers
  • Views 335 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

BQ76930: Current Measurement problem

Danijel Sipos
Prodigy 20 points
Part Number: BQ76930

Dear,

we are using for our project the BQ76930 for a 8S battery and I would have two question about it.

1. From the datasheet I am not clearly sure if I interpret good the requirements

- Under one set (VC1-VC5, VC6-VC10) can be balanced multiple cells but not adjacent. This means (in a 8S scenario) Cell 4 and 5 are allowed even if they are adjacent, but are in different sets?

2. I would have a question regarding he current measurement. The scenario:

If no load is attached the raw 16bit ADC value is 0x004F, with a Rsense of 0.5mOhms this corresponds to about +1.3A. First of all I don't know if this is correct that there would be such a enormous offset?

If I attach a load which withdraws about 0.3A the raw ADC value is 0x003F, which corresponds to about +1.063A.

If I attach a load which withdraws about 3A the raw ADC value is 0xFF88, which corresponds to about -2.0A. The absolute difference is correct but its normal that its decreasing and having the offset?

Thank you, best regards, Danijel

  • 0
    TI__Guru 54715 points

    Hi Danijel,

    1. Yes, the 4th and 5th cells in an 8 cell battery would be cells 5 and 6 for the BQ76930.  Those are in different groups and can be balanced at the same time.  Do see the interaction due to common path resistance shown in https://www.ti.com/lit/pdf/slua749 figure 8.  Cells 3 and 4 of the pack are numbered cells 3 and 5 of the IC but are adjacent in the design due to connection.

    2. 0x4F seems like a lot of offset.  Check that the CC_CFG REGISTER (0x0B) for proper setting.  Also check for leakage paths between the pack terminals.

    Load current is out of the pack and is negative by convention.  It will normally move from the offset.  Again offset should be small.  Calibrate before using the values.  Gain may need some calibration also due to sense resistor tolerance, and solder and trace resistance.