Connection problem about "PWRHOLD" pin of TPS65910 for AM3517 ?

Gandhar,

I do have problem with this PWRHOLD connection and really hope you can help to confirm it: as my understanding PWRHOLD is used to maintain Power ON status after all of power rails are up, and it should also return to zero once power -off procedure is completed. According to this it is make sense to connect this pin to VIO, but I don't understand how it could work if it connected to VRTC because VRTC is a "ALWAYS-ON" rail as long as VBAT is applied. It means PWRHOLD will never go chance back to zero unless the battery is removed. How it could be used for power control if it is done this way?

I also have problem to turn off TPS65910 even I have PWRHOLD connected to VIO(directly), simply because VIO was not fully back to zero after shunt-down process(for some unknown reason) so that PWRHOLD remain at a certain of level (about 0.8V), it causes TPS65910 back to power on status again.

Could you please help on this please? Thanks!

Jiansheng

Hello Jiansheng,

As you said, if PWRHOLD is connected to VRTC, PWRHOLD won’t go back to zero and consequently we cannot say that PWRHOLD is used for power control.

 PWRHOLD pin is usually connected to an external signal for PMIC power up/down control. If we look at the "Device state control through PWRON" timing diagram (p32 of the TPS65910 datasheet), we can notice that there is a delay (called t_dONPWHOLD) to set high PWRHOLD signal or DEV_ON control bit after NRESPWRON is released to keep on the supply.

 If you do not want to use this functionality, you can put PWRHOLD to a high level. To do it, the best way is to connect it to VRTC because it is part of its supply domain (see table exposing the terminal functions p38 of the TPS65910 datasheet).

Hope this helps,

Flore

Hello Flore Auzanneau,

t_dONPWHOLD - delay to set high PWRHOLD signal or DEV_ON control bit after NRESPWRON released to keep on the supplies.

What is the significance of the delay? if we make PWRHOLD signal high before that delay or before NRESPWRON goes to high, what will happen?

When we set DEV_OFF bit, PMIC will turn off. Is it necessary to make the PWRHOLD signal low to keep the device turn off?

If the above requirement is true to turn off the PMIC than how can PMIC_PWR_EN ( this signal will remain active till the RTC domain of AM335x is powered) signal of AM335x be used for PMIC PWRHOLD as implemented in AM335x EVM or it means AM335x EVM cannot be turn off by setting DEV_OFF.

Kindly clarify

Hello,

t_dONPWHOLD allows the processor to acknowledge the power on sequence and complete it. Indeed, after receiving NRESPWRON, the processor can complete the power on sequence by setting PWRHOLD or the DEV_ON control bit to 1. The typical value of the delay is 984ms (see datasheet p33).

It is not necessary to make the PWRHOLD signal low to keep the device turn off. If DEV_OFF bit is set to 1, then the POWER ON will be disabled.

Hope it helps,

Best regards,

Flore

Hello Flore Auzanneau,

When we set the DEV_ON bit the device will turn off once but restart again as PWRHOLD is the enable condition of the device as per my understanding( pg-41).

Can we make PWRHOLD high before NRESPWRON goes high through some external device?

Kindly clarify.

Hello,

It depends on the application. As specified in the TPS65910x checklist (available on TI website) : PWRHOLD can be connected to an external signal for PMIC power up/power down control or if control is not required, then it can be tied to VRTC. PWRHOLD can be high before NRESPWRON goes high.

Best regards,

Flore

Kindly clarify this diagram according to your explanation in above post.

Let PWRHOLD is tied to VRTC and device is  turned off by writing DEV_OFF to 1, Input power of PMIC is still present and as the PWRHOLD (connected to VRTC) is high, PMIC will start again.

Please find below the explanations of the diagram used with the state machine:

Table1:

Turn on request (to launch power on sequence) :

If one of the events listed in the following table occurs AND MB>VMBCH, the power on sequence of the device is launched unless one of the gating conditions listed in Table 3 is present.

For interrupt sources that can be configured as ON requests, see Table 4

INT1 ACTIVE means :

Table 2:

Keep on conditions

If one of the conditions listed in the following table occurs before tdONPWHOLD delay,  the device will be kept on unless one of the gating conditions listed in Table 3 is present.

with t_dONPWHOLD delay to set high PWRHOLD signal or DEV_ON control bit to 1 after NRESPWRON released, to keep on the supplies (typical value: 984 ms )

Table 3:

Turn on and keep on gating conditions

If one of the conditions listed in the following table occurs, it will prevent any switch on sequence and will turn OFF the device if in ACTIVE state.

Table 4:

Interrupts leading to Turn on request

Hoping it helps.

Best regards,

Flore

Hi Flore Auzanneau,

I want to use TPS65910 rtc as a wake up source. What are the registers I have to configure with what values so that I can use it as a RTC wakeup source.

I configured INT1 pin as active low in dts file like this:

               interrupt-parent = <&intc>;

               interrupts = <3 21 IRQ_TYPE_LEVEL_LOW>;

And in rtc-tps65910.c driver, It is configured like this:

ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,

tps65910_rtc_interrupt, IRQF_TRIGGER_LOW,

dev_name(&pdev->dev), &pdev->dev);