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Original question:

TINA/Spice/TPS50601-SP: average model, phase simulation

TPS7A4501-SP: Phase simulation: why is there a phase shift of -180° at the beginning of the graph?

user6532396
Prodigy 70 points
Part Number: TPS7A4501-SP

Dear TI community,

I just read the following topic: https://e2e.ti.com/support/tools/sim-hw-system-design/f/234/p/616938/2272973?tisearch=e2e-sitesearch&keymatch=TPS50601-SP%252525252525252520spice#2272973

Which helped me understand why there is a +180° shift at the beginning of the graph. According to the post, this is because the loop gain transfer function does not include "-1" factor due to the negative feedback at the error amplifier. Consequently, the phase margin is computed with respect to 0° instead of typical -180°.  I've tried to reproduce this example and I had the same result. This can be seen in my first screenshot below.

Nevertheless, the device I am interesting in simulating is the LDO : TPS7A4501-SP. I used the Worst-Case Analysis model. The simulation result can be seen in my second screenshot below.

So in this case, why is there a phase shift of -180°? I don't really understand, theoritically, where does this shift come from? Shouldn't it be the same as the shift for the TPS50601 simulation?

Thank you in advance for your answer.

Kind regards,

  • 0
    TI__Guru 62930 points

    I was not aware of the reason for the phase shift.   I suspected it was error in pspice or TINA algorithm to choose starting point. 

    The TPS7A4501 has positive FB into error amp, where the 50601 has negative feedback to error amp.  I believe this is reason for differing phase shift.

    The easiest solution, is to add 360 to the phase when plotting.

    If this answers your question, please click "This Resolved My Issue"
    Regards,
    Wade

  • 0 in reply to Wade Vonbergen
    Prodigy 70 points

    Thank you for your answer! I believe that make sense.

    I have another question, regarding the stability analysis. 

    My requirements for the stability is: 50° of phase margin and 6dB of gain margin

    I've simply added a resistor of 1 Ohm in series with the output capacitor to simulate the ESR of the capacitor. 

    And now my phase margin jumped from 23.73° (see my previous post) to 86.97°.

    I suspect the simulation to be wrong since simply adding a 1 Ohm resistor would shift the phase margin of + 56.27° and make my system to meet my requirements, it seems to be too easy! Am I missing something? Or am I doing anything wrong?

    Moreover, I think the gain margin computed on the graph is wrong since it is computed where the phase crosses -180°. But since the graph is shifted by -180° it should be computed where the phase margin crosses -360°, represented by the blue probe on the graph. I guess the gain margin is more something like approximately 23 dB (which seems to be a lot).

    Thank you in advance

  • 0 in reply to user6532396
    TI__Guru 62930 points

    You are welcome.

    A couple comments. 

    It was noted by a co-worker that the TPS7A4501 should have a connection to the negative terminal of error amp internally, even though the block diagram does not show this.  However, the spice model likely used the block diagram to model and since it has opposite polarity, it should account for the differing phase shift behavior. 

    To answer your question, the ESR on the capacitance should cause the behavior you are seeing with improved margin and what you are seeing should be valid.   Additionally, you can add a feed forward cap to the top leg of the Vadj divider to improve margins along with realistically modeled output capacitance.  You can reference this application note regarding Cff.

    Regards,

    Wade