• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 2 answers
  • Subscribers 62 subscribers
  • Views 362 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LM7480-Q1: Which use case does VCAP UVLO falling threshold operate?

Yoshiki Ochi
Genius 9705 points
Part Number: LM7480-Q1


Hi team, 

Which use case does VCAP UVLO falling threshold operate? 

Figure 9-1 says it keeps 12.2Vtype for VCAP-VS voltage during charge pump enabled. I wonder when charge pump voltage goes down and UVLO falling edge is detected.

In addition, could you give me the characteristics between (VCAP-VS) and VS?
I guess it is also related to charge pump UVLO falling detection case.

Regards,
Ochi 

  • 0
    TI__Guru 57737 points

    Hi Ochi,

    1. Basically, the UVLO functionality is to make sure that the FETs are enabled only after the charge pump has enough voltage to fully turn the FETs. Below is an excerpt from datasheet.
      1. To ensure that the external MOSFET can be driven above its specified threshold voltage, the CAP to VS voltage must be above the under voltage lockout threshold, typically 6.6 V, before the internal gate driver is enabled.
    2. Charge pump voltage goes down and UVLO falling edge is detected in conditions like an over loading of the charge pump capacitor.
      1. For example, if there is any condition which can cause continuous turn ON and OFF of DGATE, the charge pump may not have enough charge to  drive the gate ON and OFF for a long time and gradually the charge pump cap voltage decreases causing an UVLO event.
    3. Charge pump / (Vcap-Vs) ultimately is used to drive the DGATE and HGATE. From an application perspective, the below graphs can be more useful to you.

  • 0 in reply to Praveen GD
    TI__Genius 9705 points

    Hi team, 

    Thank you for your response. 

    Could you tell me one more additional use case for UVLO such what shown in lower? 

    Figure 9-1 looks charge pump keeps VCAP-VS within 12.2V~13.2V. What happen if VS voltage goes down to 6V?
    Does charge pump continue to make VCAP-VS 12.2V~13.2V or does VCAP-VS decrease gradually and finally trigger charge pump UVLO event?

    Regards,
    Ochi 

  • 0 in reply to Yoshiki Ochi
    TI__Guru 57737 points

    Hi Ochi,

    The valid operating voltage range of VS pin is 3V to 65V. The charge pump will function normally for VS>= 3V. 

    So, for VS = 6V, the charge pump voltage, (VCAP – VS) will still be switching between 12.2V to 13.2V.  

    The main purpose of Charge pump UVLO is to make sure FETs are enabled only after the charge pump has enough voltage to fully turn the FETs. You are asking for examples the other way round where the charge pump voltage can go below UVLO from steady state. Below are two possible conditions,

    1. if there is any condition which can cause continuous turn ON and OFF of DGATE, the charge pump may not have enough charge to  drive the gate ON and OFF for a long time and gradually the charge pump cap voltage decreases causing an UVLO event.
    2. Device Input Power Turned OFF which causes the voltages of A and VS pins to drop below their POR levels.