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Original question:

UCC21520-Q1: Gate Driver Output Resistor calculation

[FAQ] UCC21520: Parallel resitor between Gate and Source and 0V ground plane

Pablo Acuna
Prodigy 40 points
Part Number: UCC21520

Hi,

I have seen a 10kOhm resistor between Gate and Source (see R14 and R12 in the attached fig from tidue55b.pdf), but I cant figure out why the resistor is there. My guess is because measuring purposes without a MOSFET being there.

I am using a +15, -5V dual output configuration for the UCC21520.


Second question, will a ground plane in coma (S1)  or comb (S2) help to reduce noise in the gate trace form OUTA or OUTB to the SOURCE of the mosfet? I couldn't find PCB recommended guidelines for dual output sources feeding the UCC21520. In some how, RON, ROFF and the Diode are above the ground plane connected the the source as a 0-V referred to the source pin of each mosfet.

Thanks,

Pablo

  • 0
    TI__Expert 4065 points

    Hi Pablo,

    The gate to source resistor functions as a pulldown resistor that helps lower the chances of false turn on. The gate to source resistor is recommended to pull down the gate to the source voltage when the gate driver output is unpowered. This resistor also helps to mitigate the risk of dv/dt induced turn-on due to Miller current before the gate driver is able to turn on and actively pull low.

    For the second question, on the low side, a ground plane is fine so long as it doesn't go underneath the driver. For the high side, to reduce noise coupling, you should try to have shorter traces or smaller ground planes, but keep capacitors as close to the driver pins as you can. The high side plane might couple noise to the surrounding elements which is why I recommend the plane itself can be smaller or the pin traces shorter. Can you please clarify what you mean in your last sentence?

    Regards,

    Krystian

  • 0 in reply to Krystian Plaskota
    Prodigy 40 points

    Hi Krystian,

    This helped me a lot.

    Clarification: I have the UCC21520 driver with all its componets in the bottom side, but the SMD mosfet in the top. Each Output of the driver goes to a RON, which has a diode and ROFF in parallel. Just like the first picture in this post. (Taken from tidue55b.pdf)

    I can not put componentes on top layer because there is a cooper heatsink 3mm from the PCB. In the top layer I put a ground plane (cooper plane??) on each source pin opf the mosfets (0V plane B and 0V plane A), so all the negative pins of the dual source output capacitores goes there with vias. Next figure shows the ground planes on top layer.

    In the previous post, I put green text showning these two "ground planes" as 0V plane B and 0V plane A, but I made a mistake and named both of them B.

    I still can use just traces instead of the ground planes for COMA and COMB, but I beleive the ground plane will help to reduce the inductance return path for OUTB and OUTA.

    Regards,

    Pablo

  • 0 in reply to Pablo Acuna
    TI__Expert 4065 points

    Hi Pablo,

    Thanks for the additional information. I was very busy today but I will have some advice for your layout tomorrow before end of day. 

    Thanks,

    Krystian

  • 0 in reply to Krystian Plaskota
    Prodigy 40 points

    Thanks,

    Today I got the pull-down resistors at the gate. Next figure includes the resistors, and some notes.

    Cheers

  • 0 in reply to Pablo Acuna
    TI__Expert 4065 points

    Hi Pablo,

    I found this nice appnote that goes into a lot of detail about layout recommendations. I think you would find it very useful. I recommend that at least one bypass capacitor is placed directly across the supply pins and keep your traces short and close together.

    Thanks,

    Krystian

  • 0 in reply to Krystian Plaskota
    Prodigy 40 points

    Hi Krystian,

    It looks like the double source is covered there, so is going to help. I will follow these recommendations.

    Regards,

    Pablo