TPS6594-Q1: The error Reaction for MCU power error and SOC Power error is missing

Hi, Manish,

 The MCU power error means that at least one of the power rail assigned to MCU group has issue of either UV or OV error.

 Same as MCU power error, the SOC power error means that at least one of the power rail assigned to SOC group has issue of either UV or OV error.

 You can read all interrupt registers (address from 0x5A to 0x6C) to find those interrupts bits "1" to figure out the issue power rails. 

Hello Phil,

Thanks a lot for the reply. I would like to know that what is the error handling sequence when there is a MCU power error and SOC power error. There is one sequence given for immediate shutdown and orderly in data sheet.

The following sequence is explained as an example for immediate shutdown on page 121 of data sheet of tps6594-q1:

The PFSM engine can be configure to execute the appropriate error handling sequence to be
taken for the following error handling sequence options: "immediate shutdown", "orderly shutdown", "MCU
power error", or "SOC power error". For example, if an "immediate shutdown" sequence is assigned to the
MCU rail group through the MCU_RAIL_TRIG[1:0], any failure detected in this group of rails will cause the
device to execute the immediate shutdown sequence and enter the SAFE RECOVERY state. The device
will immediately reset both the attached MCU and SoC by de-asserting the nRSTOUT and
nRSTOUT_SoC (GPO1) pins. All of the power resources assigned to both the MCU and the SOC will be
shutdown immediately without sequencing order. The EN_DRV pin will be forced low, and the nINT pin
will signal a MCU_PWR_ERR_INT interrupt event has occurred

Hi, Manish,

  I'm not sure if I understand question correctly. Let me try to answer below:

  The error handling sequence when there is a MCU power error and SOC power error could be assigned as followings:

1.  Immediate shutdown. It means shutdown all power rails immediately; no order at all as its NVM assigned.
2.  orderly shutdown. It means shutdown all power in the order as its NVM assigned.
3.  MCU power error. It just generates an interrupt "MCU_ERR_INT=1"; no power rail shutdown. 
4.  SOC power error. It just generates an interrupt "SOC_ERR_INT=1"; no power rail shutdown. 

       Please see datasheet Table 5-85. FSM_TRIG_SEL_1 Register Field Descriptions for more details.

Hi Phil,

Thanks a lot again for the reply and yes your answer is in the right direction as per my question.

Our System expects the shutdown behavior but in PDN_0_A configuration it is not the expected configuration (Configured as MCU power error and SOC power error). I think we need to change the configuration so that it fits our expected system behavior.

Also, the interrupts you have mentioned in point 3 & 4 I could not find in the data sheet or PDN_0_A configuration. Any particular reason for it ?

Regards

Manish

Hi, Manish,

  Would you please search "MCU power error" and "SOC power error" again with the latest datasheet from ti.com? I can find them being described in datasheet. 

Please let me know if you still can't find them. 

Hi Phil,

Of course i can find them with 10 search elements. What i am asking is the Error Handling sequence is not described in the data sheet. For Immediate shutdown it is explained on page 121. Likewise I wanted to see for MCU Power Error and SOC Power error.

Also, It would be great Phil if you can suggest a way to do basic functionality test. From SW using I2C command I am not able to trigger the VCCA_OV condition ? Or let's say how did TI test it ? 

Regards

Manish

Hi, Manish,

  Both MCU Power Error and SOC Power error don't involve FSM (Function State Machine) and so no Error Handling sequence at all. They just generate interrupts to tell system processor that one of the power rail assigned to these groups has issue and let processor handle the error. 

 We apply high voltage (>10% of normal VCCA) to trigger the VCCA_OV condition. When it's triggered, all power rails shall be powered down, but I2C still can access the register to check if the VCCA_OV bit changes to "1". 

Hello Phil,

The Safety Manual demands the following ASIL B solution on Page 9:

The TPS6594 puts the system in a Safe State in case of failures that would lead to improper operation of the Safety-Island MCU or the SoC. These failures include:
• Failures in supply voltages to Safety-Island MCU or SoC
• Failure in input supply voltage to the TPS6594x-Q1
• Safety-Island MCU software error
• Safety- Island MCU hardware error
• SoC hardware error
The TPS6594x-Q1 has the following options to put the system in a Safe state:
• For all failures that would lead to improper operation of the MCU:
– Pull the EN_DRV pin low to disable the Actuator in the system
– Pull the reset pins of both the MCU and the SoC low
– Power-down all output supply rails
• For all failures that would lead to improper operation of the SoC
– Pull the reset pin of the Soc low
– Power-down the supply rails used by the SoC

When the VMON_CONTROLLER can do an immediate shutdown , isn't it an expensive solution for critical voltages here ? Did the above solution consider the safety aspect ?

Regards

Manish

Hi Phil,

I think i need to talk to our Safety expert to answer that. But anyways thanks a lot for your support and I really appreciate your answers.

I am closing this thread.

Regards

Manish