UCC21750: Error simulating synchronous buck circuit using UCC21750 as driver IC

Hello,

Welcome to E2E!

I can take a look into the simulation and review what could be causing the issue, but won't be able to look into it until mid-next week. Would an update by late next week be okay with your timeline?

If there's any updates feel free to post them on this thread.

Best regards,

Andy Robles

Hi,

Thanks for the prompt reply.

Though the timelines are tight it would be fine if you can help us out by mid next week.

I request to share some suggestions that we can try on our end until we get a review comment from your side.

Awaiting your response.

Thanks and Regards,

Heema

Hi Heema,

Our expert is out of office for the remainder of the week. He will get back to you with an update mid next week. 

Regards,

Krystian

Okay.

Hi,

when can we expect the support from you regarding our query?

We are running out of time.

It would be kind of you if you can respond by this weekend.

Thanks

Hi Heema,

Thank you for your patience. I will provide a response by the end of week.

Best regards,

Andy Robles

Ok. Awaiting your response. Thanks

Hi, Heema,

We have been suffering from power outages here in Dallas which is delaying some of our team members' responses.

We will reply to your questions early next week.

Okay. Please reply as soon as possible. WE are running short of time.

Thanks.

Hi Heema,

Thank you for your patience. As Don mentioned, the unexpected events in Dallas last week caused some delays. I will get back to this as soon as possible. Expect an update by EOD tomorrow 2/23 CST.

Best regards,

Andy Robles

Hi,

Thanks. Awaiting your response.

Caliber, 

The issue appears to be with your Top driver U1 controlling the ON phase FET. 

U1 secondary side should not be referenced to the same ground as U2, but i see several instances where this is occuring. 

U1 COM should be connected to the SOURCE of the ON phase FET, not VEE. 

Please remove all references to low-side / primary side ground on U1 and fix the VEE/COM connections.

Best

Dimitri

Hi Dimitri,

We have incorporated the changes as suggested by you.

Please find all the modification details and snapshots of Circuits & waveform in the attachment.

After making the changes, simulation is not converging and after 26% simulation stops.

Please advise.

Thanks,

Girishhttps://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/196/6675.TI.7z

Hello, 

Your primary sides of BOTH ICs need to be grounded, along with the secondary side 

Additionally, you have essentially shorted the Outputs of both driverss as well as some signals on the primary side. When you use the same Label, the nets become shorted. 

Please fix the grounding and shorting. 

I would recommend to restart yourschematic without the inductor/ FETs and just monitor the outputs of the drivers until the simulation is running and gate driver outputs are right.

Then you can add the buck topology back in with teh inductor and FET. If the simulation cannot converge when there are just 2 drivers , this is much easier to fix early on without having the extra complexity of the inductor and fet models. 

Best

Dimitri

Hi Dimitri,

Thank you for your continued support and quick response.

We have incorporated the changes as suggested by you.

Please find all the modification details and snapshots of Circuits & waveform in the attachment.

After making the changes, we run simulation without connecting FET and Inductor and checked pulses and it converged.Simulation is taking more time if we connect inductor and FET.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/196/TI-updated-response01.03.21.7zPlease check and advise.

Hi Dimitri,

Thank you for your continued support and quick response.

We have incorporated the changes as suggested by you.

Please find all the modification details and snapshots of Circuits & waveform in the attachment.

After making the changes, we run simulation without connecting FET and Inductor and checked pulses and it converged.Simulation is taking more time if we connect inductor and FET.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/196/2656.TI-updated-response01.03.21.7zPlease check and advise.

Hi,

Looking at the schematic there are some minor edits I would make to the schematic. The high side gate driver instead of creating a reference net SW connect the COM pin to the 0V reference ground through a 100MOhms resistor. For the low side driver do the same for COM or connect COM directly to the 0V ground. Example shown below.

The 2 edits mentioned above seem to sped up the simulation by half although it is still taking a long time to complete the simulation.

Let us take another look at it and get back to you by tomorrow with an update.

Best regards,

Andy Robles

Hi Andy,

Thank you for your quick response.

We have incorporated the changes as suggested by you.

Please find all the modification details and snapshots of Circuits & waveform in the attachment.

Also we have done our own changes which speed up simulation and kindly check and give your advice.

Kindly suggest us on 1. how to connect DESAT if we are not using it?

                                   2.What are the changes to be made in TI for pspice if circuit is not converging.

Thank you,

Girishhttps://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/196/TI-updated03.03.21.7z

Hi Caliber,

I will get back to you with an update by EOD tomorrow 3/3. Thank you for your patience.

Best regards,

Andy Robles

HI Dimitri,

Thank you for suggestions.

1.Currently we have tied DESAT to COM via 1k resistor.

2.If we use ideal mosfet with ideal inductor in TI for pspice circuit is converging.

   a.But output is very low compared to expected output.

   b.We are getting around 230V than 580V according to duty ratio set.

c.If we use our mosfet model with 10MEG ohm resistor in place of inductor simulation taking more time.

d.Hope its necessary to connect 100MEG ohm resistor with com of U1 and U2 driver because as observed if not connected simulation is hanging.

e.Kindly check attached source files, circuit pdf,snapshots of settings.

Kindly advice.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/196/TI040321.7z