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TPS543B20: upper limit on the input clock freq when operating in stackable mode

Adam Daluga
Expert 6385 points
Part Number: TPS543B20
Other Parts Discussed in Thread: TPS543C20, TPS543C20EVM-869

Hello,

We are considering using the TPS543B20 in stackable mode in one of our designs in order to make use of the phase shift functionality of the part.  The synchronization frequency we would like to provide as the clock is nominally 1 MHz, but with tolerances, could be slightly in excess of 1 MHz.  Do you know if there is an upper limit on the input clock frequency of the TPS543B20 when operating in stackable mode?  It would appear that the 1 MHz value listed in the datasheet is the maximum allowable value, but I would like to confirm this if possible.

Thanks,

Adam

  • 0
    TI__Genius 17905 points

    ,

    1MHz is the upper limit specified by datasheet, but I would not be too concerned if the clock source is ~tens of kHz on the high side above this. It is not a hard limit where the part will simply not function with a slightly higher clock. You would have to evaluate your design to see if performance is acceptable. If you have the ability to replace ICs, I recommend getting the TPS543C20EVM-869 and replacing the TPS543C20 (40A part) ICs with TPS543B20 ICs to evaluate your stacking design condition with your external clock source, to check if things like regulation, transient, SW jitter, stability are acceptable for your application.

    Regards,
    Kris