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UCC21732-Q1: FLT and RDY Fault

user6304068
Prodigy 45 points
Part Number: UCC21732-Q1
Other Parts Discussed in Thread: UCC21732

Hi, 

Recently I have met several problems when using UCC21732 isolated gate driver IC in our 3-phase motor controller product(which has adopted SiC MOSFET). 

FLT and RDY Falt:

1. FLT or RDY fault was often observed in motor drive production qualification test(occurred 5 times in the past 1000 products), and I think this could be a false alarm.

2. When I intentionally create short-circuit cases to test the de-sat protection functions, RDY fault was also sometimes observed.

So which conditions could possibly cause such phenomena? could it be caused by radiated EMI? since this chip has a very strong CMTI capability against conducted EMI.

De-sat blanking time setting:

I noticed there exists a deglitch filter of 150ns inside the chip. So for blanking time calculation, should I also take this extra 150ns for consideration? for example, if I set 100ns blanking time using the RC circuit, then the total real blanking time should be 250 ns...

Layout issue for high side SiC MOSFET:

In the datasheet, there you can find layout guidelines: " if the gate driver is used for the high side switch, which the COM pin is connected to the switch node, ground plane is not recommended". What was the reason behind this guideline?  In addition to that, I find in the application note "SLUUBX2A", a ground plane was used...

Looking forward to your reply ：） 

BTW, do you also have a local service person who could help us onsite? (in China). if yes, please contact me :)

best regards,

He

  • 0
    TI__Genius 10652 points

    He, 

    user6304068 said:

    FLT and RDY Falt:

    The source of this is difficult to determine without additional details about the design. Are you seeing significant ringing at the gate during turn-off/DESAT soft turn off?

    user6304068 said:

    De-sat blanking time setting:

    UCC21732 has OC pin (which can also be configured to act as DESAT). Have you configured it to function as DESAT? OC may be more effective for SiC overcurrent situations. 

    user6304068 said:

    To answer your question, the deglitch time is NOT added to the blanking time youve setup with the capacitor. Deglitch time just there to ensure that only "valid" OC/DESAT conditions are considered, e.g. the threshold needs to be exceeded for the deglitch time. Transients on OC pin which are shorter than the deglitch time are thus ignored. 

    Layout issue for high side SiC MOSFET:

    This layout recommendation is very important to avoid coupling the highside COM node to the large ground plane. The COM is connected to the highside source/emitter which has a very high dv/dt and can capacitively couple. 

    user6304068 said:

    BTW, do you also have a local service person who could help us onsite? (in China). if yes, please contact me :)

    TI has Shanghai office and several others in China. I expect they would have reached out to you by now if you had purchased the ICs from TI directly. 

    Does your company have a Field salesperson or Field engineer assigned to your account? THey would be the first point of contact. 

    Please let us know any further questions. 

    Best

    Dimitri

  • 0
    TI__Genius 13650 points

    Hi He,

    Welcome to E2E!

    In addition to Dimitri's comments, given the failure rate of the issue it might be a bit difficult to determine what could be causing the FLT and RDY assertion issues mentioned in your post. In order to provide more accurate possible root causes I would like to first take a look at the schematic and layout if possible.

    I have sent you a friend request through this E2E forum with my email in order to share the schematic and layout as I understand that is probably confidential information. We can continue our conversation through email.

    Best regards,

    Andy Robles

  • 0 in reply to dimitri james
    Prodigy 45 points

    Dear Dimitri,

    "To answer your question, the deglitch time is NOT added to the blanking time youve setup with the capacitor. Deglitch time just there to ensure that only "valid" OC/DESAT conditions are considered, e.g. the threshold needs to be exceeded for the deglitch time. Transients on OC pin which are shorter than the deglitch time are thus ignored. "

    We used the OC pin and set the threshold as around 8 V. I understand what you mean by deglitch time.  In this case, the real  "blanking time“ for OC detection is the blanking time set by capacitor + 150ns deglich time: after gate turn on, Vdd needs firstly to charge Cblk to be above 0.7V, then during the following deglitch time (which is 150ns) the OC pin needs to hold above 0.7V, then this case could be identified as FLT case. 

    I don't know if I understand this correctly ：）

  • 0 in reply to user6304068
    TI__Guru**** 189399 points

    Hi, He,

    Unfortunately, your image didn't post correctly. Can you try again?

  • 0 in reply to user6304068
    TI__Genius 13650 points

    Hi He,

    Your understanding of the deglitch time is correct "after gate turn on, Vdd needs firstly to charge Cblk to be above 0.7V, then during the following deglitch time (which is 150ns) the OC pin needs to hold above 0.7V, then this case could be identified as FLT case".

    For further assistance feel free to post waveforms and schematic on this thread, or email to the address I gave you in my friend request.

    Best regards,

    Andy Robles

  • 0 in reply to Andy Robles
    Prodigy 45 points

    Dear Andy,

    I have sent our schematic and layout regarding this problem through email. Pls help to check if there is an inappropriate design.

    Many thanks!

    Best regards,

    He

  • 0 in reply to user6304068
    TI__Genius 13650 points

    Hi He,

    Absolutely. I will review the schematic and reply to your email.

    Best regards,

    Andy Robles