TPS546D24A: Power Good operation during AVIN/PVIN power application

Bradley Higgins

Part Number: TPS546D24A

Engineering desires to use the TPS546D24A AVIN/PVIN common input voltage, 3.3V, as the pullup source for the PGD pin.

Am I correct to assume that if I follow the IPGD test condition that the Power Good specification , 0.8V shown below, will be maintained until the POR completes.

Spec indicates PVIN is already at 12V and AVIN at 0V, just trying to verify that there will not be any spurious indications of PG while device is powering up.

This would equate to an ~33.3K ohm resistor from 3.465V (max input rail voltage) to limit current to 80uA if the PGD pin is 0.8V.

(3.465V-0.8V)/80uA = ~33.3K ohm

Thanks,

Brad

over 4 years ago

0 Vincent Zhang(BSR) over 4 years ago

TI__Expert 4795 points

Hi Bradley,

We are looking into this and will feedback to you next week. Thanks.

0 Peter James Miller over 4 years ago

TI__Guru 56775 points

Bradley Higgins

Yes, you are reading the specification correctly The PGD pin includes an internal "self-bias" circuit that connects external PGD pin to the gate of the internal pull-down to turn-on the pull-down FET if the PGD pin is pulled up, even if AVIN is 0V.

Once there is sufficient voltage on the AVIN pin to power the PGD pull-down FET driver, the internal FET will be driven harder and the PGD voltage will be lower.

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TPS546D24A: Power Good operation during AVIN/PVIN power application