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TPS2H000-Q1: architecture on OUT to GND

Part Number: TPS2H000-Q1

Hi Team, 

my customer  met one failure on this part then we do some tests to try to find the reason and need your explain on below questions. 

1. what's the internal architecture between OUT pin and GND pin, is there a ESD diode? 

when no Vs power supply, adding -32V on OUT pin, then the part is broke. 

But when Vs is supplied but the part is disabled, adding -32V on OUT pin, then the part still works. So customer want to know if there is real ESD diode between OUT pin and GND pin or there is a switch between those pins. 

2. based on the failure, the body diode of internal MOS is damaged. Then will OUT pin to GND also be shorted ? 

Thanks. 

BRs

Given

  • Given,

    We have a good application note that talks about loss of supply and loss of ground and some of the design considerations:
    https://www.ti.com/lit/pdf/slvaes9

    There is no ESD diode on the output, however there is a high impedance (~200kΩ) from OUT to GND. If there is a potential for negative voltages on the output with a loss-of-supply the recommendation is to have a resistor/diode network on the ground pin as suggested in Figure 36. Reverse-Current External Protection, Method 2 in the datasheet. 

    What is the nature of the load? Are there any significant inductances?

  • Hi Timothy,

    Thanks for your reply. 

    Customer just see the body diode of the internal MOS is damaged, then they do some tests and find negative voltage on OUT pin will make damage. so they ask the questions. The load doesn't have significant inductance. 

    BTW, what's the current capability of the body diode of the internal MOS? Thanks. 

    BRs

    Given 

  • Given,

    We do not spec the body diode of the FET.

    If there is not an inductance on the load- where is the negative voltage coming from. A loss of battery + negative voltage (above what the device is rated for) is considered a double fault and operation would be unreliable at this point. There is an ESD diode on the input of the device so if enough of a negative voltage was placed on the output this could potentially bias via the ESD diode, however any such voltage would be an egregious violation of the device's spec'ed limits.