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TPS61288EVM-064: 2.0V input

FRANK1
Expert 8555 points
Part Number: TPS61288EVM-064
Other Parts Discussed in Thread: TPS61288

Hi sir,

I use evaluation board  tps61288 evm-064 now.

The circuit is changed so that the output voltage becomes 6V.

If the output load of the power source is only the load (12 ohms), the input voltage is driven even if the input voltage is 2.0 V,

but if the output load of the power source is connected to the load (12ohm) in parallel with the cap 200uF, the circuit will shut down when the input voltage becomes 2.7V or less.

Can you tell me to adjust which parts value in the circuit, so that the Min 2.0V can drive this requirement.

Thanks.

  • 0
    TI__Mastermind 34231 points

    Hello Frank,

    Thanks for reaching out.

    May I know what's the 200uF cap part number and ESR value? You need to consider the ESR zero frequency effect on the loop stability for this design. You may need to re-design the compensation parameters.

  • 0 in reply to Zack Liu
    TI__Expert 8555 points

    Hi Zack,

    Thank you for replying.

    Please find my power schematic below.

    power schmatic.pdf

    Thank you.

    Regards,

  • 0 in reply to FRANK1
    TI__Mastermind 34231 points

    Hi Frank,

    Thank you.

    TPS61288 input rising UVLO is 2.4V maximum and falling UVLO is 2.0V maximum. 

    As the voltage 2.7V is very close to TPS61288 input UVLO spec, please make sure the power supply cable are short and wide enough to avoid large voltage droop on it. 

    You could use a DMM or probe to check Vin pin is higher than VIN UVLO first. Could you also share the VIN, SW, VOUT pins waveform?

  • 0 in reply to Zack Liu
    TI__Expert 8555 points

    Hi Zack,

    I found the reason as that the system side embedded with the evaluation board was shut down at 2.7V.

    I cancelled it and it's normal now.

    Than you for your suggestion.

    BTW, I wanna know more about C3&C4 on the output of EVM board.

    Why you use C3&C4 and what are their functions?

    Thanks a lot.

  • +1 in reply to FRANK1
    TI__Mastermind 34231 points

    Hi Frank,

    Glad to hear the good news.

    C3, C4 are all output capacitors in parallel with C5~C9. You could design the output capacitance based on output ripple, load transient undershoot and overshoot requirement. 

  • 0 in reply to Zack Liu
    TI__Expert 8555 points

    Hi Zack,

    We are trying to reduce the noise emitted from the power supply circuit.
    It is necessary to suppress ringing.

    I try to add resistor on BST terminal to drop the switching speed.

    Is there a problem with this use for this IC?



    Or except for the spare pattern of the snubber circuit provided on the evaluation board

    Is there any other method?

    Thanks a lot.

  • +1 in reply to FRANK1
    TI__Mastermind 34231 points

    Hi Frank,

    There are below methods to reduce the switching noise:

    1. Add snubber circuit from SW pin to GND.

    2. Place a 1uF 0603 package ceramic cap as close to IC as possible. Please see output ceramic capacitor C3 position on EVM.

    Since the SW node noise mainly happens when low-side FET turns on/off, the resistor in series with bootstrap cap affects the high-side FET turn on/off time, so it has little effect on noise reducing.