normally, we will set PFC current loop bandwidth to below 5khz. Do you have details about the reason? Thanks.
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actually there is no standard that current loop should be below 5kHz.
For analog PFC controller, it is able to increase the current loop higher than 5kHz.
For digital controller, because of the calculation delay, it is a little bit to increase the PFC current loop up to 5kHz, and a lot of real design just set a 1-2kHz current loop.
with higher current loop bandwidth and still keep system stable, you may be easy to achieve a good PF/ITHD performance,
and with lower current loop bandwidth, and by adding zero crossing compensation to reduce the zero crossing distortion can also achieve a good PF/ITHD performance.
system stable and PFC performance meet its system requirement are always much important than whether the loop bandwidth is high or low.
hope this answers your question.