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UCC21750: RDY pin intermittently tripping

Tom Farkas
Prodigy 10 points
Part Number: UCC21750

We have several half-bridge SiC modules on each of two boards, each driven by a pair of UCC21750's.  The RDY pin on the low-side drivers occasionally goes low (and latches the driver off for about 0.7ms).  VCC-GND=3.3V, VDD-COM=15V. and VEE-COM=-3V.  Probing of the supplies shows 15 MHz ringing noise from the hard-switched FET drain, but the 3.3V supply remains above 3.0V and even the dips to 3.0V are brief as the ringing lasts only a few 100 ns, much less than the 10us deglitch time specified on the datasheet.  (Switching frequency is 30 kHz).  The isolated 15V supply has similar or better margin.  Raising the 3.3V supply to 3.75V somewhat decreased the occurrence of the RDY trips (by about a factor of two) but did not eliminate it.  Margining the 15V supply by +/-1V did not impact the occurrence.  Is there something else besides VCC or VDD undervoltage that can cause RDY to go low?   Our dv/dt is about 10V/ns (400V/35nS).  Is there some noise sensitivity in the chip that can over-ride the deglitching?  Is it possible that the VCC is internally dropping below the undervoltage threshold without it appearing so low at the external VCC pIn?

  • 0
    TI__Genius 13760 points

    Hi Tom,

    Welcome to E2E!

    Typically UVLO conditions on VCC or VDD should be the only reason the RDY signal would trigger. The only other condition I can think of that could possibly cause this abnormal behavior would be by the switching transient noise causing the voltage to exceed the abs max rating of some pins of the the gate driver. In order to provide further assistance I would like to request some more information:

    1. Would you be able to share the schematic configuration of the UCC21750? (A schematic of one low side gate driver would be fine. I can also share my email through the E2E messages if there's confidentiality issues)
    2. Could we capture some waveforms showing RDY trigerring?
      1. Below are the critical signals that could help us find the root cause. Make sure to use a small probing loop in the measurement to capture the most accurate representation of the signals feeding into and out of the driver. Use the scopes full bandwidth and sampling rate(>1GS/s preferred).
        1. RDY-GND
        2. VCC-GND
        3. OUTL-COM
        4. VDD-COM

    Let me know if there's any questions.

    Best regards,

    Andy Robles

  • 0 in reply to Andy Robles
    Prodigy 10 points

    Yes, please email me or provide your email address for further data sharing.  I do have one follow-up question I can post though, as changing out the IC seems like it may have eliminated the problem.  We previously operated the chip for quite some time (including many startups) with a 100 ohm resistor from the APWM output to a 100nF filter cap.  This was before we noticed the 20mA abs max current rating of the APWM pin.  With no significant DC loading on the filter cap, we would only violate the 20mA rating on startup by drawing 33mA initially.  We also noticed that the APWM amplitude in steady state with the 100 ohm/100nF filter was only about 2V.  After changing the resistor to 10K, the APWM output amplitude was 3.3V as expected.   I was skeptical of having damaged the chip as a result of this operation, but we recently swapped out the chip and the UVLO (RDY pin) issue may have been eliminated.  Perhaps it's just a UVLO threshold tolerance, but I'm wondering if it's possible that the brief overloading of the APWM pin could have damaged the chip and caused the RDY tripping issue.

  • +1 in reply to Tom Farkas
    TI__Genius 13760 points

    Hi Tom,

    I have sent you a friend request to your profile through the E2E forum with my email so you can share the schematic if you would like.

    In your email you mention that the chip had been operated for quite sometime including many start-ups.

    • During those previous tests or start ups did the RDY signal ever trigger?
    • Did RDY only start randomly triggering or did it start happening after a certain test?

    Exceeding the abs max specs of our drivers could result in damaging the device. I do not have previous history of the driver causing this RDY trigger due to exceeding the current rating of the APWM pin, but since it is exceeding abs max it is a possibility.

    If the driver did not show this RDY trigger issue before, and then started triggering RDY under the same previously tested conditions then it is likely at some point the device got partially damaged due to exceeding abs max. If possible it would be good to capture the same signals mentioned in my previous email on the known unit that triggers RDY and on the unit that does not to see the difference between both drivers.

    • RDY-GND
    • VCC-GND
    • OUTL-COM
    • VDD-COM

    Best regards,

    Andy Robles

  • 0 in reply to Andy Robles
    TI__Genius 13760 points

    The schematic was reviewed over email and there was a couple items that could be improved upon to increase the gate drivers noise robustness. This thread will closed as the conversation will continue over email.

    Best regards,

    Andy Robles