We have several half-bridge SiC modules on each of two boards, each driven by a pair of UCC21750's. The RDY pin on the low-side drivers occasionally goes low (and latches the driver off for about 0.7ms). VCC-GND=3.3V, VDD-COM=15V. and VEE-COM=-3V. Probing of the supplies shows 15 MHz ringing noise from the hard-switched FET drain, but the 3.3V supply remains above 3.0V and even the dips to 3.0V are brief as the ringing lasts only a few 100 ns, much less than the 10us deglitch time specified on the datasheet. (Switching frequency is 30 kHz). The isolated 15V supply has similar or better margin. Raising the 3.3V supply to 3.75V somewhat decreased the occurrence of the RDY trips (by about a factor of two) but did not eliminate it. Margining the 15V supply by +/-1V did not impact the occurrence. Is there something else besides VCC or VDD undervoltage that can cause RDY to go low? Our dv/dt is about 10V/ns (400V/35nS). Is there some noise sensitivity in the chip that can over-ride the deglitching? Is it possible that the VCC is internally dropping below the undervoltage threshold without it appearing so low at the external VCC pIn?