BQ76952: Stacking two ICs

Hi Manuj,

I have seen other users stack two devices, but they usually use low-side FETs do to the complications using high-side FETs with a stacked solution. 

A more detailed description of the DSG FET driver for the BQ76952 is shown in Section 16.5 of the datasheet. The DSG pin will eventually get pulled well below VSS of the top device since it will follow the PACK+ voltage (which will go to GND of the system). 

This presentation shows a basic block diagram for stacking two of these devices using low-side FETs: How to stack non-automotive protectors and monitors in high-cell-ccount applications.pdf

Dear Matt,

Thanks for your reply. What you have mentioned about the DSG FET driver, does this apply to the PDSG driver and CHG driver too? If not so, I may still be able to use the PDSG and CHG driver of the top IC and have some other arrangement for driving the DSG MOSFET for high side switching.

This does not apply for the PDSG and CHG drivers, so it may be possible to drive these from the top IC. The most challenging aspect will be controlling the DSG FET. 

There are some other things to keep in mind with stacking:

- The upper device will not detect current, so the body diode protection feature needs to be thought through carefully. 

- SLEEP mode is entered automatically when the measured current falls below a programmable threshold. This means the upper device would always be in SLEEP mode if allowed, so the host will need to control this carefully. 

- Isolation will be needed to communicate with the upper device since the comm pins will be referenced to the upper device VSS.

Best regards,

Matt

Dear Matt,

The presentation on stacking in the web-link has the following connection for the load detection functionality for the stacked configuration

• Could you please help me understand how the load detection and charger detection functionality works in this? Load detection functionality should be implemented on the lower IC since it is the one sensing current and has to recover from SCDL and OCDL faults,
• Should I follow the exact schematic for load detection but without low side MOSFETs for load detection, given that I am using top IC for CHG and PDSG driver and some other high voltage MOSFET driver for driving DSG
• As in the PACK and LD pin connection shown in the diagram above, wouldn't Pack pin of the top IC be subjected to voltages lower than the VSS of the top stack incase of short circuits and other load conditions? If it does, will it happen for both high side and low side switching? 

Thanks and Regards

Manuj Agrawal

Hi Manuj,

In the diagram shown from the stacking presentation LD of the top device is connected to the part's VSS (or cell 16), so the load detect will not work on the top device, it will always be loaded and recovery would need to be from some other mechanism.  PACK of the bottom device is connected to the same cell 16 point, here that is about the supply voltage potential for the IC.  Load detect for the bottom part is provided by the transistor which senses the PACK- voltage.  For the top device any fault recovery should not depend on load detect.  Since the part does not sense current that is likely a low risk. For the bottom part it does sense current and could protect from OCD or SCD.  The designer may not want to recover into a SCD condition, so load removal could be selected for a recovery condition.   

• Load detect and charger detect:
  • Load detect: After SCD or OCD the bottom device will pull up on its LD pin to check for load removal.  If a load is present which raises the PACK- voltage toward the PACK+ voltage the external transistor will clamp LD to VSS.  PACK- must come almost back to the VSS level (about 2 x Vgsth of the external FET) to turn off the external FET. With the external FET off the part can pull up LD to its internal level across its threshold and recognize the load "removed".  As you may have noticed in the low side drive apnote if the CHG is left high during the fault the charge FET drive will go through the charge FET Rgs resistor and hold PACK- up to near the drive voltage and prevent turn off of the external LD transistor preventing recovery, so CHG will need to be turned off.   
  • Charger detect:  The circuit above does not have a charger detect feature. Connecting a charger during the OCD/SCD condition without turning off the charge FET would force PACK- low and cause load removal detection, but not specifically a charger detection.  A special circuit would be needed to detect charger attachment from a signal, a measurement of the PACK- pin voltage or a comparator feature with an appropriate threshold.
• With high side MOSFETs the load detection circuit must be different.  The device is designed for LD to sense PACK+ through a 10k resistor.  With low side switching the load removal logic is inverted by the external FET shown in the diagram above.  With high side switching the inversion is not needed, but you need to protect the LD pin from excessive voltage excursion.  One possibility might be a 10k and diode from the bottom LD pin to PACK+.  The measurement would pull the pin low, during OCD/SCD fault the part would pull up on LD and the diode would pull down to PACK+, if PACK+ was held at/near PACK- the load would be detected.
• Manuj Agrawal1 said:

  As in the PACK and LD pin connection shown in the diagram above, wouldn't Pack pin of the top IC be subjected to voltages lower than the VSS of the top stack incase of short circuits and other load conditions?

 No, during a short circuit assuming 0 resistance in the short, interconnect and FETs, PACK+ = Cell16 = GND (battery-).  PACK pin of the top part would be at its VSS.  LD of the top part is still at its VSS.  PACK pin of the lower part is at Cell16 which is at its VSS, LD of the bottom part is pulled to VSS by the external transistor. These were checked in the system design for the figure shown.  When implementing a high side stacked system similar checks should be done. In general during the short circuit timing the voltages will be ok, after the FETs open be sure voltages don't pull to unsafe levels, for example the upper PACK pin could not pull to the battery- level 16 cells below its VSS. 

As Matt indicated in the thread above the body diode protection based on current and the load detection based on current may make FET control from the part with current detection preferred.  You won't have that if you split the drivers with the top controlling the charge and the bottom controlling discharge. Think through the control carefully to accomplish your design needs.

Dear Matt and WM5295,

Based on our discussion on stacking and high side switching, I assume that following should be the connection for MOSFET drivers, LD, PACK and VSS pins of the two ICs

Here, I am driving the CHG and PDSG MOSFETs through top IC and DSG MOSFET through another custom high side MOSFET driver

• Please let me know if the connection for LD pin with 10K resistor and diode to PACK+ for lower IC is correct as per your previous reply
• I am still unsure about how to connect PACK of the top IC since Matt already mentioned that voltage at the PACK pin (and hence DSG pin) of the top IC might go to the GND of the system and thereby pulled to a voltage below the VSS of the top IC. Can you please help me with this?
• Moreover, are rest of the connections correct?

Thanks and Regards

Manuj Agrawal

Hi Manuj,

1. Yes, the lower LD looks like my suggestion.  It will likely read an odd voltage since PACK+ can't pull it up.  During current fault recovery the part can pull the pin up to its internal test voltage and PACK+ can hold it down through the diode as needed.  For a small additional voltage margin you may want a Schottky type diode.

2. The top PACK pin could be tied to the cells like the lower, or if you want to sense a charger voltage with the pin you could connect from PACK+ through a diode and 10k to the top PACK pin.  PACK+ can pull the pin up to almost the PACK+ voltage when PACK+ is at the 16 cell voltage or higher, but when at the 16 cell voltage or lower the diode will block current out of the PACK pin and it should give a near 0 V indication.   Adding a Schottky from the PACK pin to VSS also would avoid the pin pulling low from leakage or capacitance of the diode to PACK+ when it is held at the PACK- level.

3a.  In general yes, realize the slides you viewed as well as your diagram are simplified diagrams.  Include filter components & limiting resistors as needed.  For example the bottom PACK pin can connect to the 16th cell as shown, but a 10k resistor is recommended for the pin.  Since the cells can have transients it would be good to keep that 10k in the PACK connection.  For the top IC LD is connecting to the VSS of the IC.  There should be no transient between LD and VSS, so connecting with 0 ohm should be fine.  Connecting LD to VSS with the normally recommended10k resistor would also be fine.

3b. The pre-discharge connection to the top part will work fine for the signal levels since it controls the FET with respect to the BAT level.  However it will normally coordinate with the DSG output which is not used in your diagram.  Determine how you will use it in your system.  Predischarge can be controlled based on LD voltage which is not appropriate here since LD is tied low, or based on a timeout.  See the settings in the technical reference manual section 13.3.6 Settings:FET.  

3c.  The "custom high voltage high side driver" for the discharge FET control will need some control system.  Since you have a complex system I would expect it to include an MCU.  Options would seem to be:

• The top IC, (DDSG) perhaps not appropriate since it does not detect current, but has the predischarge control (included in the DDSG output)
• The bottom IC, (DDSG) perhaps critical since it has the current sensing inputs for fast SCD response
• The MCU which would know the desired system state.
• Some combination of the above to consider the system state with the fast response of the current sense comparators and the state of the upper part.

There are many ways to do the driver and they won't necessarily be the same for every system.  Work out what is appropriate for your system. 

Dear WM5295 and Matt

Thank you so much for your help through quick responses. Based on the discussion, here is what I think the connections should be

1. I have updated the PACK pin connection for the top IC with two diodes as you mentioned. Please check if this is what you meant in the previous reply

I will keep in mind that these diagrams in the PPT are very abstract and for basic understanding. Actual circuit would be much detailed :) I would also take care in control logic for the mosfet drivers and will go through all the fault cases and their impact on mosfet on/off logic during fault and recovery

Thanks and Regards

Manuj Agrawal