Hello expert,
Does TPS54425 have regulation for Vin start up time?
Thanks and best regards,
Ryo Akashi
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Hello expert,
Does TPS54425 have regulation for Vin start up time?
Thanks and best regards,
Ryo Akashi
Akashi-san,
To reach regulation (desired VOUT), the VREG5 which is derived from VIN needs to be above 3.8V typ which is the UVLO threshold. Some other factors like VIN ramp time and how that relates to the soft-start time and if the VOUT can reach regulation before 1.7xSS time or not is also something that needs to be checked. Let me know if there is any specific requirement or any more questions.
Thanks,
Amod
Hello Amod-san,
Thank you for your reply.
Let me ask onw question about 1.7xSS time.
In datasheet P8 "Over/Under Voltage Protection" section, there is description about "This function is enabled approximately 1.7 x softstart time."
Could you tell me start point of "1.7 x softstart time"? This time (1.7 x SS time) start from after Vin enter?
Thanks and best regards,
Ryo Akashi
Akashi-san,
As soon as EN is logic HI and VREG5 > 3.8V typ (wake-up voltage), SS-time should start. You need to ensure SS time is long enough (size CSS appropriately) that VOUT is in regulation after 1.7x SS time else the UVP protection could kick in and latch-off both FETs.
Thanks,
Amod
Hello Amod-san,
Thank you for your reply. I understand that SS-time should start after EN become High and VREG5 exceed 3.8V(typ).
In datasheet example, Css=3300pF, then SS-time is about 1.26ms.
Also, if desired Vout is 5V, we need to exceed 3.5V(VUVP threshold : 5 x 0.7) in 2.145ms (1.7 SS-time) to prevent UVP detection.
It's not good for VIN slow ramp up after exceeding 3.8V because there is possibility to detect UVP.
So, "fast VIN ramp up which can meet Vout regulation in 2.145ms" or "Using large capacitor to ensure long SS time" is needed.
Is my understanding correct?
I would appreciate if you would give me comment.
Thanks and best regards,
Ryo Akashi
Hello Amod-san,
Thank you for your reply. Let me ask one more question for UVP.
If UVP protection kick in and latch-off both FETs, how do we recover from this state?
Thanks and best regards,
Ryo Akashi
Hi Akashi-san,
You will need to reset VIN and EN to recover from the latch-off.
Thanks,
Amod
Hello Amod-san,
Thank you for your reply and I'm sorry for my late reply. I got it.
And let me ask one more question.
If we use larger capacitor, we can set longer SS time but there is no effect except SS time. Is it correct?
Thanks and best regards,
Ryo Akashi
Akashi-san,
larger output cap with short SS time can cause over current during startup. You can size the SS cap to ensure the startup is smooth without current limit issues.
Thanks,
Amod
Hello Amod-san,
Thank you for your reply. I forgot to say about cap detail. I mean the cap connected with SS pin(SS cap only).
From functional block diagram in datasheet, SS cap is only connected with Soft Start function. So, if we change SS cap value only, there is no impact except SS time. Is my understanding correct?
Thanks and best regards,
Ryo Akashi
Akashi-San,
yes that is correct. SS cap only affects SS time.
Thanks,
Amod
Hello Amod-san,
Thank you for your advice and I'm sorry for my late reply. I understand SS cap only affects SS time.
Let me ask one more question.
Is there any regulation for SS cap value? In datasheet, 3300pF is used.
If there is maximum value or other requirement (e.g. capacitor type), could you tell me?
Thanks and best regards,
Ryo Akashi
Akashi-san,
There is no limit on the SS cap value mentioned in the datasheet. So, you can try higher values for your application.
Thanks,
Amod
Hello Amod-san,
Thank you for your reply. I got it.
Thanks and best regards,
Ryo Akashi