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TPS56C215: TPS56C215 Pspice model mismatched with datasheet

Guillaume BASTIEN
Prodigy 20 points
Part Number: TPS56C215


Hello,

I am using the TPS56C215 buck regulator and after simulation, I am facing a bug in the model.

The schematic :

 

The simulation : 

The problem is that P_GOOD2 (yellow) pin is "HIGH" when the output (pink) start rising.

I think there is a mistake in the model or something wrong in my simulation.

Thanks for help me

  • 0
    TI__Expert 7500 points

    Hi,

    I have simulated just now and I also met this PG wrong results. There should be something wrong with TPS56C215 Pspice model. I will check with our team.

    The description in datasheet should be right. Once the FB pin voltage is between 93% and 107% of the internal reference voltage (VREF) the PGOOD is de-asserted and floats after a 200 μs de-glitch time.

    Thanks,

    Lishuang

  • 0
    TI__Expert 7500 points

    Hi,

    I have submit a request to modify the Pspice model which will take several days. I also double checked on our EVM, the PG behavior is matched with DS description. So I will close this thread first if you have any other questions, you can re-open or submit a new thread.

    Thanks,

    Lishuang