LM5117: Failing EMC by 16.67dB at 213MHz

Hi Daniel,

As you mentioned, the SW copper and vias should be minimized, and the high dv/dt traces (SW, LO, HO) should be routed internally. See app note snva803 for power stage layout best practices, especially in terms of input cap placement where the GND return is routed below the FETs to minimize the power loop parasitic inductance.

My recommendation here is to remove the external VCC connection and run from the internal 7.5V VCC. The implies a lower gate drive amplitude, which will inherently reduce the dv/dt on both the SW voltage and gate drives. Check also that the correct terminal of the inductor is tied to SW (typically the inside of the winding is the dotted end, and this is effectively shielded by the outer turns connected to VOUT).

Regards,

Tim

Hello Tim,

I was trying to follow figure 2 in that document. As for routing the traces, I saw no mention of that in the documents. In the third example, they route LO and SW on the top. I only have 4 planes, Should I be run them in the VCC plane?

I am not using an external VCC connection. Those parts are DNP. I left them there in case I needed to to do. As for the inductor, there is no internal winding, it is only a stack going upwards. https://datasheet.ciiva.com/22680/1681984-22680336.pdf?src-supplier=Element14

Regards,

Daniel

Hi Daniel,

This is a very large, unshielded inductor with a large radiating area. For 10uH /~10A, it's possible to find a more compact/shielded design. At the very least, ensure that the lower winding turn is tied to SW. Take a look at the LM5145 datasheet for PCB layout guidelines as that has more relevant detail compared to the LM5117 documentation.

By the way, what is the VCC plane here? Typically, GND is a better option as it is adjacent the bottom layer (which faces the EMI table). One option is to cover the radiating copper or vias with a large electrolytic cap (for example an input cap for damping, etc.)

Regards,

Tim

Hi Timothy,

How do I tell if an inductor is shielded. The title of the datasheet is "Shielded Power Inductors - SER2900" what do I need to look for. One of the reasons I choose that inductor is thermal issues, the size pulls heat from the low side fet which was getting super hot when I used a smaller one. I checked and the lower winding is connected to SW. 

As for the LM5145 documentation, yes that is what my design follows. The component placement is as close as I can make it to the example , particularly in the power section. I am not able to place components on the solder side. One thing I can do is move the controller closer to the switches but not by much. There are also minor errors with the vias for the gate drives. They are 16mil instead of 20mil but I have two of them.

As for the stackup, please see the stackup image. The ground plane is under the component side as was suggested by the datasheet. 

I am sorry but I don't follow covering up the radiating copper or vias with copper. Am I not doing that?

Regards,

Daniel

Daniel,

The idea is to cover up radiating surface with an electrolytic cap to provide shielding - we use this technique in the LM25149-Q1 EVM. Even ceramic caps over a radiating via provides some benefit. However, the dominant effect here is likely the inductor. A shielded inductor has a winding surrounded by core material - see the Coilcraft XAL1010-103 molded inductor as an example. This is much smaller and should provide significant benefits in terms of the radiated signature.

--Tim

I accidently clicked resolve. I will try what you mentioned above. The EMI sniffer probe is highest in the inductor area. I have used higher Cboot resistor (5.6R) but lowered it because it did not make a difference and the high fet was running really hot.

I will test the conducted emissions.

The mosfets I am using are:

High Side CSD18543Q3AT

Low Side CSD18533Q5A

Daniel

Hello Timothy,

My board is currently scheduled for the conducted emissions test to see if the problem is arising from there. The lab was able to reduce the emissions to pass levels by adding oversized ferrits to the output power wires (they are as short as possible and were twisted). This is not really a viable solution going forward.

The changing of inductors did not seem to have an effect.

I have also decided that a board re-spin might be in order. I went with the layout suggested in figure 3 of snva803. I do have some questions though about ground planes and fill.

My board has all components on the top (I cannot place on solder side of board). So the stack up is:

1) Components (with ground fill)

2) Gnd

3) Vcc

4) Solder side (with ground fill)

Now my question is should I remove the ground fill on the bottom and top layer near the inductor? I am worried about magnetic fields inducing high currents because of the vias and ground fills/planes creating loops.

Also, should the decoupling caps for Vout be near the coil or the electrolytic.

Thank you for your help.

Hi Tim,

It was suggested to add a ferrite to the gate of the FETs. I cannot find an example of this in literature and would like your opinion.

Thanks,

Daniel

Thank you Tim, that was my argument as well. I needed a third party confirmation.

Cheers,

Daniel