Hi all...please help my weary eyes out but it looks to me that the datasheet for the TPS61178RNWR has an error...maybe?
11.2 Layout Example
The FET is a P-Channel, part number: Si7633DP per webench, but it looks to me like the S's and D's are backwards in the layout drawing.
What say you?
https://www.vishay.com/docs/69008/si7633dp.pdf
Might I suggest a closer look at the 11.2 Layout Example on page 30 of the datasheet and compare that to the datasheet of the p-channel fet. There are no 4 source pins and 3 drain pins...
Ken
Hi Wood,
I understand your questions now.
As our EVM used the PMOS CSD25404Q3, which has four source and three drain pins, we used similar footprint in layout example.
It doesn't matter how many source and drain pin that the PMOS you select.
