TPS2663: FLT signal

Hi Yamaguchi,

Is it happening at light loading of the motor ?

Can you please share the customer schematic and test waveform of Vin, Vout, Iout, FLT during that event.

Best Regards, 

Rakesh

Hi Rakesh-san,

I asked the customer to share the schematic and the test waveform, but they declied it because the information is confidential and difficult to submit easily. I explained in the text below. Could you please check the contents first? If the schematic or waveform information is essential to solve the issue, I will try to get it again.

I told you that the issue occurs on +24V rail, but it was wrong information. The customer is seeing the issue on +5V rail.

- Fault firing situation of 5V efuse:
In customer's setup, when two boards of the same type are used and powered from the same power supply, a 5V fault fires on one board.

The power supply to the two boards is via the backplane, which is the same power supply network.
However, there is naturally a slight difference in wire length of a few centimeters between the boards.
The phenomenon also gives the impression that the board closer to the power feed connector fires a fault.

- Fault firing timing:
The fault signal goes from "L" to "H" in about 10ms after Vin=5V starts up, and the device starts normally for a while.
However, about 2ms later, the signal goes from high to low, leading to the fault firing.
However, even though the device is in latch-off mode, the output is not shut down when the fault is fired.

- The customer's circuit multiplier:
R1=110k, R2=6.8k, R3=33k, R4=240k, R5=82k
RLIM=2.7k+3.3k=6k
FLT signal: pull-up at 10k (pull-up at 3.3v, generate 3.3v from 5v)

With these values, the following settings are made.
IOL:3A, OV:3.03V, UV:4.52V

- Customer's circuit outline
No diode in the first stage of IN1 and IN2.
No external FET configuration (open without B_GATE and DRV)
IN_SYS pin: Connect 5 V as is.
MODE pin: Open to set to latch-off mode.
SHDN pin: Open.
PGOOD: Open
OUT1, OUT2: Output 5 V through noise filter + 100uF capacitor.

Additional question : Based on the 9.2 Function Block Diagram, can you provide a truth table of the conditions that lead to fault firing and latch-off mode?

Regards,

Yamaguchi

Hi Yamaguchi-san,

Please share the schematic and test result details via email. That helps to understand better and do debug. Please do the needful

Best Regards, 

Rakesh

Hi Rakesh-san,

Sorry to my late reply. I have not obtained the waveform, but I was able to narrow down the question. Could you please help with the questons below?

I would like to know the following specifications when a pulsed overcurrent exceeding the IOL setting occurs.
(1) FAULT firing operation specification.
(2) Latch OFF operation specification.
What kind of current waveform and how long does it take for FAULT and latch OFF to occur, or is it ignored?
I would like to know these operation specifications.

The following is the background for the questons above.

-When observing the current waveform, two pulsed current waveforms exceeding iol (3A) are observed.

-The pulse current waveform of the first bump is Iout_peak = 4.6A (pulse width = 100us)

-The pulse current waveform of the second bump is Iout_peak = 4.3A (pulse width = 100us)

-The time interval between the two pulse current waveforms is 400us.
At this time, FAULT occurred on 1/2 of the boards, and Vout output decreased. (It drops from 5V to about 3V and then returns to 5V again. No latch off)

-However, if the time interval between the two pulse current waveforms is shorter than 400us, e.g. 200us, FAULT will not occur.

Regards,

Yamaguchi