UCC28730 DC to DC Converter

Hello Eric,

Thank you for your interest in the UCC28730 flyback controller.

The UCC28730 is designed to achieve a regulated constant current at the output once the Iocc target is reached. As the load resistance is decreased, output current stays regulated and output voltage falls.  To do this, an internal control loop regulates the off-time duty cycle to 0.432 (Kcc factor). 

Using the design method that you propose will result in regulation of the output voltage up to the Iocc target (30W/15V = 2A, in this case), but it will not limit there.
If the load increases higher than this, output current will continue to go up until the off -time D = 0.432.  This may be 3~5X what you expect for Iocc.

In your equations, you are implicitly assuming an independent method of current limit, so the P=1/2LI^2f equation could stand on its own.
However with this controller, Ipk has to satisfy two simultaneous equations, equation 14 as well as equation 6, and further check equations 18 and 19.
Following the UCC28730 design procedure in correct order will ensure that Iocc is achieved, but with you high input voltage, it will require a large inductance value and high turns ratio.  Your method will work only if you don't care what the current limit is.

The UCC24650 wake-up IC is not required for regulation, but it does help keep the size of the output capacitance down.  If your application does not require extremely low standby power and/or stringent step response, then the UCC24650 is not necessary. 

Regard,
Ulrich

Hello Eric,

Your question on fres reminded me of another point about determining the magnetizing inductance.  Part of the procedure is to first determine Dmax in equation 10.  Here, Dmagcc is fixed at 0.432 and fmax is chosen by the designer.  In the text we suggest to assume 2us for tr, but that is typical for the lower-voltage 90Vac~264Vac systems.  We have found that with higher input voltages, Lp is much higher and in turn, the DCM resonance period 2pi*sqrt(LpCswn) is longer than 2us.  This reduces Dmax, which then influences Nps and Lp calculations.  The trouble is that it is an iterative process, since Dmax and Lp are interdependent, and may require a few calculation passes to converge.  I mention this because it can help bring Lp and Nps down a little bit.

Since the high voltage and higher Lp brings fres down, it may be difficult to ensure compliance to Equations 32 and 33, since reducing Cswn means using a higher-resistance MOSFET.  On the other hand, the 15V output can drive a significant wake-up signal, so there may not be a concern in this particular case.  The UCC24650 datasheet will provide guidance on this situation. 

If the UCC24650 is not used, the UCC28730 cannot react to any change on the output until its next switching cycle happens.  As a PSR controller, it only samples the output voltage at the end of the demagnetization period of each switching cycle.  In a no-load situation, the UCC28730 is capable of switching at very low frequencies (down to ~32Hz) so worst case there may be a ~30ms wait-state lag before the controller can detect and respond to a load step.  Without the wake-up chip to eliminate this lag, the system must rely on much larger output capacitance to hold up the output voltage until the next switching cycle occurs.  An alternative to the UCC24650 is to add a pre-load to the output that increases the minimum fsw and reduces the wait-state time between samples.  Of course, the pre-load raises the input stand-by power, so there may be a trade-off to be made depending on your Pstby target. 

Regards,
Ulrich