• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 64 subscribers
  • Views 920 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS53667: tps53667 system is very unstable and the damage rate is high

user5006944
Intellectual 630 points
Part Number: TPS53667

The TPS53667-based power solution we have used now finds that the system is very unstable and the damage rate is high after working for a period of time.

1)The damaged chips are in the singular position. We don't know if the samples are not enough. Now There are  9;
2) We have read the power chip through PMBUS and started to stop working when the temperature reaches 100 degrees Celsius, but many chips are burned out, and all the burned chips look the same as the burning position. I am looking for A burnt one that  can be seen clearly

the Schematic is below.Can you help me to analyze and solve the problem?

tps53667sch.pdf

  • 0
    TI__Intellectual 1790 points

    Hi,

    Would you please provide  layout files also for review.

    • From figure, Power stage CSD95490 damaged. please describe test conditions. VIN,VOUT, load, room temapetarure,?
    • provide PMbus telemetry report/snapshot also before damage or staeady-state.
    • at steady-state, is the temperature >100C?. and power stages are damaging after turn-off.
    • is always Phase1 power stage damaging?

    Thanks.

    Regards,

    Rama.

  • 0 in reply to Rama Pamidi
    Intellectual 630 points
    layout is review by TI. so should be ok.

    Vin =12V,Vout=0.7V,Iout=240A,Tc=30℃
    no use PMbus before damaging,so use PMBUS to set 100,but also damaging
    Maybe at steady-state, the temperature is >100C
    not only Phase1 power stage damaging, is always Phase 1/3/5 power stage damaging.
  • 0 in reply to user5006944
    TI__Intellectual 1790 points
    Thanks for feedback.
    we know, layout reviewed by TI. But need to double confirm, thermal vias are properly placed for thermal distubution beacuse perphase steady state current >=40A.
    we requested PMbus GUI snapshot, to check current sharing equal per phase at 240A load or any unbalace.
    please provide SW node waveform(without filter on probe), to check peak ringing voltage at SW node.

    Regards,
    Rama.
  • 0 in reply to Rama Pamidi
    Intellectual 630 points
    Tomorow I will send the waveform to you ,Now I found the damage powerstage lead to the short of VIN. more and more boards are damage . When I turn off the power .then turn on the power, the boards are also damage.Please help to analyze and solve the problem.Thanks a lot.
  • 0 in reply to user5006944
    TI__Intellectual 1790 points

    Hi,

    would you please send us the waveform and also layout files.

    Thanks.

    Regards,

    Rama.