BQ76PL455A-Q1: Expected jitter on ADC results?

Hi Taylor;

See 8.1.3.1 Idle (Parking) Channel Errors.

I checked to ensure that as per the datasheet, the AFE_CTL bit = 1 - and it is by default. Our driver requests ADC results every 1.000 seconds, and maintains a Max/Min log. And as I mentioned, my client has 3 other eval boards (EM1402), and tested at least one other for this using the SW  GUI provided, and the results are the same...

This is what we're seeing on the top cell #13 (the worst):

[12] 0x20003360 (AFEChanStruc + 384) 

CalAvgFloat     4.05372905 V
MaxV               4.05395794 V
MinV                4.05166912 V
MaxDelta         2.28881836E-3 <-- results vary as much as 2.9mV, which is ~76.3uV (LSB) x 38, meaning over 5 lsb's of jitter

Also, please find attached a log of the test results using the EMV and its GUI. It shows the same behavior.

TI_190104_152515_00.xlsx

Yes, they're tied to cell 13. This design is using the 455 because its predecessor(s) (EMB1432, EMB1433, etc.) went obsolete and are no longer available. So the cell harness ties the unused cells together.

TI_190110_120933_00.xlsx

Hi Taylor; Attached is the noise my client sees while the GUI is triggering conversions. Is this expected? 

Also, the attached GUI-generated spreadsheet shows 0's for AUX channels, yet each is tied to VIO through 20K's on the eval board? I believe it shows all channels enabled, but I've tasked them with resetting to 13 and retest.

Attached is the image of the noise we got measuring across C40 (VDIG & GND). Previously, at address 7 (Command Oversampling) I had a value of 0x7D which does 32 sample averages and attached are the results of the log file. I can try writing a value of 0xFD to see if that makes a difference.

Active_Chipset_Reference_Design_Guide.pdfHi Taylor; Hope they're paying you overtime ;-D.

I see an interesting change on the EM1402 from it progenitor, the EM1400 (The "Cheetah"):  

I note that the filter Caps on the Vsense lines all tie to AGND, rather that to the adjacent cells, as it's done on my client's existing BMS, which uses the same AFE input filtering as did the EM1400.  It's confusing as to why this was done on the 1402,  because now  each Vsense line filter will have differing characteristics???

I note that your latest application guide (SLUA791A) of 10/2018 says:

" For applications that require a very low filter cutoff frequency, connect a differential (?) capacitor between the VSENSE lines to provide the bulk of the AFE input filtering. The bias voltage on these differential capacitors are the same (or very close), therefore, anti-aliasing is improved."

I "think" this reference to a "differential capacitor" is confused, and it merely means a capacitor between the cells, just as was originally done. Nevertheless, curious as to why this changed since my client's AFE is much quieter and uses the original NatSemi components. What is more, the zeners are on the post-filter side? If I recall correctly, zeners are noisy. This may not be contributing to the jitter, but it's curious?

see:  TI Active Chipset Reference Design Guide Revision: 1.5 Apr 26, 2012 5.1 Fig. 3

5658.Active_Chipset_Reference_Design_Guide.pdfHi again Taylor;

 I just saw something different in the Vsense filter circuit between the EM1402 and its progenitor, the EM1400 (the original "Cheetah" that used the now obsolete EMB1432 AFE):

I note that the filter Caps on the Vsense lines all tie to AGND, rather that to the adjacent cells, as it was originally done, and is done in my client's legacy BMS. That's really odd because each Vsense line filter will have differing characteristics

I note that your latest application guide SLUA791A of 10/2018 says:

" For applications that require a very low filter cutoff frequency, connect a differential (?) capacitor between the VSENSE lines to provide the bulk of the AFE input filtering. The bias voltage on these differential capacitors are the same (or very close), therefore, anti-aliasing is improved."

What is more, the zeners are on the post-filter side, which might have been changed due to hot-plugging inrush (?). However, if memory serves, zeners are notoriously noisy. Whether they're contributing anything measurable to the jitter, I don't know.

See attached Sec 5.1 Fig 3 describing the orignal

Hi Roger and Taylor;

Please see the attached captures. I'm really confused as to why there are ~2V glitches on OUT during sampling, since all channels are sitting at the same voltage, +/- a few millivolts??   Note jpg 101625 which captures the incoming command sent on Chan2, followed by the sequence of cell acquisitions at 60us intervals (sampling successive cells, not the same one)… See also jpg #102259 which shows OUT close up.

Is this expected behavior?

Thanks