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UCC256302: Power management forum(Regarding the conditions under which Vgs is output)

user6350145
Prodigy 30 points
Part Number: UCC256302

When the burst operation is exited, dV/dt cannot be confirmed and operation is being performed by the ISNS pin.

At this time, when the waveform of the ISNS pin reaches the inflection point, the gate of the high side FET will turn on.
I thought that the gate on the high side would turn on at the inflection point on the lower side of the ISNS pin voltage. Is this correct?
The timing when the high-side gate turns on differs between the normal product and the abnormal product with respect to the waveform of ISNS.
When the FET is turned on by the voltage of the ISNS pin, is there a cause that the timing shifts like the waveform sent?
Is there a factor other than ISNS that causes the high-side gate to turn on differently?TI_Inquiry.xlsx
  • 0
    TI__Guru* 85696 points

    Hello,

    During normal operation, I believe you are correct that the high side FET turns on when Isns is negative.

    However when both FETs turn off during burst mode their is ringing in the primary and to stop the transformer from saturating the opposite gate turns on when coming out of the burst.  If the Isns polarities are incorrect the UCC256302 will adjust the timing until the high side and low side gates are triggered with the proper Isns current polarities.

    So when coming out of a burst packed it is possible for the gate drive to turn-on when the Isns pin has the long polarity.  However, as you waveform shows this is generally correct in three switching cycles.

    Regards,

  • 0 in reply to Mike O'
    Prodigy 30 points

    Hello,

    In the waveform of the normal product sent, the gate is on when the ISNS pin voltage is high.

    When you exit Burst Mode, the gate may turn on when ISNS has a long polarity. Is this the reason why the gate turns on when the ISNS pin is high?

    What are the conditions under which this mode occurs?

    Regards,

  • 0 in reply to user6350145
    Prodigy 30 points

    Hello,

    Could you answer the question asked on June 9th?
    Regards,
  • 0 in reply to Mike O'
    Guru 11170 points

    Hello Mike,

    I think that the question is " why different operation for between two devices on recovery from burst-mode ".

    I would like to hear from you.

    Regards,
    ACGUY

  • 0 in reply to user6350145
    TI__Guru* 85696 points

    Hello,

    I have researched this further.  The ISNS pin is used to detect over current and not does not control were the HO and LO FETs turn on during normal operation.  This pin monitors the current will shut down the FETs on over current conditions. 

    The voltage on the VCR pin actually controls the turn off of the high side and low side FETS based on a 3V common mode voltage and the voltage on RFB.  Please refer to the attached slide that explains this.VCR Controls Turnoff of the FETs.pptx

    The UCC256302 will monitor the switch node and turn on the HO and LO FET when zero Volt switching is detected at the switch node.  Please note that delay of the Turnon of these FETs is also adjust internally by the UCC256302 to ensure there is not too much body diode conduction.

    Please study your waveforms again in regards and look at the VCR pin and FB pin voltage and FB current,  you should be able to determine the gate drive turnoff of the HO and LO FETs

    Regards,