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LMG5200 low side FET third quadrant conduction

Other Parts Discussed in Thread: LMG5200

HI,

I am working on a project with LMG5200. 

I carefully read through SNOSCY4B (TI document for LMG5200) and found that in page 10,  it said 

"HI and LI can be independently controlled to minimize the third quadrant conduction of the low-side FET for hard switched buck converters"

 

The document is talking about a third quadrant conduction when Low side SW is turned off and conducting a reverse current? ( like a body diode)

(In a synchronous buck converter, I think Low side SW should operate in third quadrant to replace the diode when it is tuned on.)

Thank you.

  • Hi Jongwan,

    yes you are correct, the third quadrant operation is similar to a body diode conduction as far as current direction and gate state are concerned.

    GaN HEMTs don't have a body diode, therefore this mode is caused by the gate voltage being biased by Cdg/Cgs  which turns on the FET in the linear region and keeps the voltage at the Drain constant.

    In the LMG5200 this voltage is at 2V.

    Therefore if you have current flowing from the source to the drain while the gate is off, you can equate this with a body diode that has 2V of forward bias. This mode of conduction is suboptimal, and want to minimize this by turning on the gate as soon as possible, thus minimizing the dead time.

    Best regards,

    Alberto

  • I have a one more question.

    what can be the minimum dead time for LMG5200? I chekced the document from LMG5200 Evaluation board and there was a waveform with 7~8ns dead time.

    7~8ns can be a minimum dead time for LMG5200?

    Thanks
  • If you fine-tune the dead time, you can get it down to about 2ns safely. I would recommend to check your waveforms for mismatch and verify over temperature .
    Regards,
    Alberto
  • Hi Jongwan,

    I would like to offer a clarification: when I was referring to the 2ns dead time I was referring to a hand-trimmed solution in a constant temperature environment.

    If you are trying to ensure that under all conditions and across various parts/ boards you don't run the risk of shoot-though, you should design it around the maximum mismatch, which is specified at 8ns.

    Hope this helps.

    Best regards,

    Alberto