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Need info on setting Ct when using dV/dt control on TPS24720 Hotswap controller

Rick Hille
Intellectual 410 points
Other Parts Discussed in Thread: TPS24720, TPS24750

Using TPS24720 hot-swap controller in a 12V 10A application with dV/dt control on the MOSFET Gate per the suggested alternative design example in the datasheet. Predictably, the inrush TIMER times out and shuts the MOSFET off too soon into power-up when using a Ct value of 47nF based on P-lim determined T-on (Step 4 in datasheet), but we can't find a calculation for determining Ct when using dV/dt control. Power-up succeeds by doubling the Ct value, however, this may not be enough under all conditions, and making Ct too big may risk the MOSFET SOA. The TPS24720 EVM (SLUU458A) has Ct of 68nF in parallel with a destuffed 2.2uF, and has a MOSFET Gate dV/dt network, also destuffed.  Presumably the 2.2uF is stuffed when the Gate network is installed, but there is no mention of how the larger Ct is calculated.

Is there any more info for using the device with dV/dt limited gate control?  I'd like to see the suggested calculation approach for Ct if there is one. 

  • 0
    TI__Mastermind 42795 points

    Rick,

    Within the last month, TI has removed the dV/dt startup text from both TPS24720 and TPS2471x datasheets primarily because of the better FET SOA protection feature contained in this controller family. Additionally, there are problems that can arise when using dV/dt startup when a hot short is applied to the circuit output. Please see the attached report for more explanation.

    If the application really requires dV/dt startup, I would suggest using the TPS24750/1 design calculator tool (http://www.ti.com/lit/zip/slvc545) to help with the equations and number crunching. Cell C71 on the Design_Calculator tab provides the equation to size Ct and cell C42 provides a choice of dV/dt or power limited startup. TPS24750/1 is a TPS24720 based controller and TI FET in a single package. The EVM design may be just what you are looking for (12V/10A design).TPS2471x-20 GATE Capacitor Inrush Control.pdf

  • 0 in reply to Eric Wright
    Intellectual 410 points

    Thanks for letting us know the very recent status of this particular mode of application, which can be revised in our design with some simple BOM changes.

    Removing the dV/dt network, the main output risetime of 3-4msec is now roughly half what it was, and appears slightly rippled (less than 0.5V pk-pk) through the 30-70% slew region.  Ct was restored to 47nF and its startup voltage ramps to just under 1V before starting the discharge slope.   One noteworthy observation, however, is that the capacitor voltage exhibits a sharkfin shaped oscillation (fast-fall, slow-rise) of approx. 200mV pk-pk at 160usec cycle-time (6.25KHz) riding the charge-up slope, in apparent sync with the ripple seen on the main output slope.  It doesn't look at all like the clean slope in Figure 29 of the 24720 datasheet, and sort of hints at a potential loop stability issue during SOA protection regulation.  

    The gate output has a reverse-Vgs voltage protection network (zener clamp) which adds 20-ohms series and some parallel diode junction capacitance to the MOSFET, a CSD16403Q.  Could that be responsible for the output ripple observed?  It is strange that it also shows up on the Ct voltage, given that the internal block diagram shows that the only means of charging and discharging the cap is through a couple 10uA current sources.