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AM625SIP: PDN Via Sharing

Calex36
Intellectual 2345 points

Part Number: AM625SIP

Tool/software:

I have a PDN related question about AM625SIP. I went through most of the documentation HW related available online, and am pretty confident we can work with it. We would use 6 layer PCB and closely space the PWR/GND planes respectively.

What I am trying to evaluate now is the following:

Implementation Examples and PDN Targets Table 7-6, mentions max L per cap is <1.5nH for AM62xx, admittedly it is not the SIP, but a similar table for SIP does not exist.


Another app note, covering the fanout, AM62x SiP Escape Routing for PCB Design, section 5 Via Sharing, shows a way how to fanout the VDD_CORE and how the actual footprint of the BGA has been thought/designed with via_sharing in mind. However, traces shown on the image(snapshot from above app note), already add >1.2nH in trace itself leaving almost an impossible margin for the PDN(sandwich of pwr/gnd + decoupling). 



It seems like two recommendations, from different perspectives, contradict each other. 

 

Do you have internal success with "via sharing" or is the PDN target set to be too cautious OR a SIP variant can be more "relaxed" in terms of PDN?”

  • 0
    TI__Guru**** 211480 points

    Hello Calex,

    Thank you for the query.

    Let me review the inputs and check with the team internally.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Guru**** 211480 points

    Hello Calex,

    Refer inputs i received:

    The Target impedance for AM62x and AM62xSiP will be identical as the same worst case load transients exist on both designs since they share the same die.

    Via sharing recommendations in the escape application note are only made to help guide a customer to escape the design with fewer vias in the VCA regions. The number of vias used for escaping signals will ultimately depend on the specific customer use-case, the number of interfaces that need to be implemented and the layer count. If the specific use case allows the customer to use more vias for VDD_CORE in the VCA regions, that is definitely a valid approach. Per-pin loop inductance guidelines are more applicable for single-pin supplies that are connected to a decap. In case of multi-pin supplies like VDD_CORE where there are a number of parallel connections to multiple pins/decap thru multiple vias, it is hard to tie it back in to a per-pin requirement. The most important target to meet is the impedance target specified in Table 7-6 of the PDN Applications note. This table is the same for AM62x and AM62x SiP.

    Regards,

    Sreenivasa