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[FAQ] How to flash GPMC-NAND with Lauterbach JTAG on AM62x

Hong Guan64
Guru 62785 points
Part Number: AM625
Other Parts Discussed in Thread: SK-AM62-LP

Tool/software:

AM62x boot rom supports booting from parallel GPMC NAND.
From "5.4.9.1 GPMC NAND Bootloader Operation" in AM62x TRM
"GPMC NAND boot only supports boot from ONFI 1.0 compatible 8 bit parallel NAND memory up to 2Gbytes in size connected to GPMC CS0 with the following geometries:
• 2Kbyte page and spare area of at least 64 bytes or
• 4Kbyte page size and spare area of at least 128 bytes.
• Non-ECC part only:
– ROM uses ELM to handle ECC
– ECC is BCH8 using D[7:0] for data
– The param page CRC is checked and in case of failure the redundant page is used"

Please refer to AM62x TRM "Chapter 5 Initialization" for details on GPMC NAND support by boot rom.

The FAQ lists how to flash u-boot to GPMC NAND with Lauterbach JTAG on SK-AM62-LP board [1] and [2], and provides an alternative flashing option in addition to the u-boot based approach [3][4], and is useful for initial SoC bring-up…
[1]. SK-AM62-LP board (https://www.ti.com/tool/SK-AM62-LP)
[2]. TI internal NAND card (PROC143E1)
[3]. https://e2e.ti.com/support/processors-group/processors/f/791/t/1402705
[4]. https://e2e.ti.com/support/processors-group/processors/f/791/t/1460090

  • +1
    TI__Guru 62785 points

    1. Generate ECC(BCH) on Linux host
    - The Linux host tool to generate ECC: bin2nand
    - How to run the tool

      Usage: bin2nand [options] input output(input+bch) output(bch)
  Options: 
    -type raw|one        - NAND type, default: raw
    -page 512|2048|...   - Page size, default: 2048
    -spare 16|64|218|... - Size of the page spare area, default: 64
    -block 16|32|64|128  - Block size (number of pages), default: 64
    -verbose             - Print ecc's. 
    -corr <sector>       - Generates correctable error(s).
    -uncorr <sector>     - Generates uncorrectable error(s).
    -bigspare            - Spare area size = page size (Denali).
    -badblock            - Marks blocks as invalid.
    -bch 8               - Use BCH as ECC algorithm.
                           Error correction capability is 8 bits only.
                           If not set, then no ECC is used.

    - An example run

    ./bin2nand -page 4096 -spare 256 -block 80 -verbose -bch 8 tiboot3-gpmc.bin tiboot3-nand_bch.bin tiboot3-gpmc_bch.bin

    2. Lauterbach T32 scripts on flashing GPMC-NAND on AM62x
    - Lauterbach T32 scripts: am62x_gpmc-nand_u-boot.zip
    - A sample T32 flashing log on “SK-AM62-LP + NAND daughter card”: am62x_nand_flash_u-boot.log

    bin2nand

    am62x_gpmc-nand_u-boot.zip

    am62x_nand_flash_u-boot.log 
    ======================================================
7. Oct 2024
GPMC_NAND flashing on TI SK-AM62-LP + NAND daughter card
==> BOOTMODE[15:0] = 025B for GPMC-NAND booting
--------NAND FLASH---------
Manufacturer = MICRON(0x2C) , Device ID = 0xD3 (0xD0, 0xA6, 0x66, 0x0)
---------NAND ONFI---------
[0:3]Parameter page signature: ONFI
[4:5]Revision number: 0x2 0x0
[6:7]Features supported: 0x1A 0x0
[8:9]Optional commands support: 0x3F 0x0
[32:43]Device manufacturer: MICRON      
[42:63]Device model: MT29F8G08ADAFAH4    
[64]Manufacturer ID: 0x2C
[65:66]Date code: 0x0 0x0
[80:83]Number of data bytes per page: 0x0 0x10 0x0 0x0
[84:85]Number of spare bytes per page: 0x0 0x1
[86:89]Number of data bytes per partial page: 0x0 0x4 0x0 0x0
[90:91]Number of spare bytes per partial page: 0x40 0x0
[92:95]Number of pages per block: 0x40 0x0 0x0 0x0
[96:99]Number of blocks per unit: 0x0 0x8 0x0 0x0
[100]Number of logical units: 0x2
[101]Number of address cycles: 0x23
[102]Number of bits per cell: 0x1
[103:104]Bad blocks maximum per unit: 0x28 0x0
[105:106]Block endurance: 0x1 0x5
[107]Guaranteed valid blocks at beginning of target: 0x8
[108:109]Block endurance for guaranteed valid blocks: 0x0 0x0
[110]Number of programs per page: 0x4
[111]Partial programming attributes: 0x0
[112]Number of ECC bits: 0x8
[113]Number of interleaved address bits: 0x1
[114]Interleaved operation attributes: 0xE
[128]I/O pin capacitance: 0x8
[129:130]Timing mode support: 0x3F 0x0
[131:132]Program cache timing: 0x3F 0x0
[133:134]tPROG maximum page program time: 0x58 0x2
[135:136]tERS maximum block erase time: 0x10 0x27
[137:138]tR maximum page read time: 0x19 0x0
[139:140]tCCS minimum: 0x64 0x0
[164:165]Vendor-specific revision number: 0x1 0x0
[166:179]Vendor-specific: 0x0 0x0 0x0 0x2 0x4 0x80 0x1 0x81 0x4 0x3 0x2 0x1 0x30 0x90
[248]ECC maximum correct ability: 0x0
[249]Die select feature: 0x0
[254:255]Integrity CRC: 0x99 0x32
======================================================
FLASHFILE erase done.
file 'C:\T32\DMxx\lauterbach\HG\am62x_burn_flash\gpmc-nand\binary\tiboot3-gpmc.bin' (Binary) loaded. 324358 bytes.
file 'C:\T32\DMxx\lauterbach\HG\am62x_burn_flash\gpmc-nand\binary\tiboot3-gpmc_bch.bin' (Binary) loaded. 20480 bytes.
FLASHFILE erase done.
file 'C:\T32\DMxx\lauterbach\HG\am62x_burn_flash\gpmc-nand\binary\tispl.bin' (Binary) loaded. 1207371 bytes.
file 'C:\T32\DMxx\lauterbach\HG\am62x_burn_flash\gpmc-nand\binary\tispl_bch.bin' (Binary) loaded. 75520 bytes.
FLASHFILE erase done.
file 'C:\T32\DMxx\lauterbach\HG\am62x_burn_flash\gpmc-nand\binary\u-boot.img' (Binary) loaded. 1295899 bytes.
file 'C:\T32\DMxx\lauterbach\HG\am62x_burn_flash\gpmc-nand\binary\u-boot_bch.bin' (Binary) loaded. 81152 bytes.