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[FAQ] AM625 / AM623 / AM620-Q1 / AM625-Q1/ AM625SIP / AM62A7 / AM62A3 / AM62A1-Q1 / AM62D-Q1 / AM62P / AM62P-Q1 / AM62L Custom board hardware design – Queries regarding LVCMOS Digital Clock Source for, MCU_OSC0 (WKUP_OSC) or WKUP_LFOSC0 (LFOSC0)

Part Number: AM62L
Other Parts Discussed in Thread: AM620-Q1, AM625, AM623, AM625-Q1, AM625SIP, AM62A3, AM62A1-Q1, AM62A7, AM62D-Q1, AM62A7-Q1, AM62A3-Q1, AM62P-Q1, AM62P

Tool/software:

Hi TI Experts,

Can you share the external LVCMOS Digital Clock Source specifications and guidelines while using external LVCMOS clock input as the processor clock source for

MCU_OSC0 (WKUP_OSC0 for AM62L)

WKUP_LFOSC0 (LFOSC0 for AM62L)

 

  • Hi Board designers, 

    The FAQ is generic and can also be used for

    AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1 processor family

    AM62A7 / AM62A7-Q1 / AM62A3 / AM62A3-Q1 / AM62A1 / AM62A1-Q1 and AM62D-Q1 processor families.

    AM62P, AM62P-Q1 processor family

    AM62L processor family

    Refer below inputs:

    External LVCMOS clock specifications:

    Data Sheet reference 

    MCU_OSC0 LVCMOS Digital Clock Source Requirements

    Note: The table is added for quick reference. refer to the data sheet for the updated information.

    Datasheet

    AM62Dx Sitara Processors datasheet

    https://www.ti.com/lit/pdf/sprspb5

    Refer processor-specific data sheet for the required information.

    The Specification in the data sheet is currently being updated.

    Follow the above specification in case the specifications are not available in the data sheet.

    Connection of LVCMOS clock input

    1.8V LVCMOS-Compatible Clock Input

    The clock inputs are not fail-safe

    The clock inputs are referenced to 1.8V, VDDS_OSC0.

    The Clock input is not fail-safe

    It is recommended to connect the Oscillator supply to the same supply that is connected to the VDDS_OSC0

    Is there any concerns using LVCMOS clock input

    Using a crystal to create a reference clock for AM62x family of processors is preferred because there is less risk of clock jitter issues.

    There is no concern using LVCMOS clock input. Follow the above specifications while selecting the oscillator. If you use a LVCMOS oscillator, select one that doesn't contain a PLL. LVCMOS clock sources that only implement a crystal oscillator operating in fundamental oscillation mode provides lower clock jitter than one with a PLL.

    Ensure you follow the Note added in the MCU_OSC0 LVCMOS Digital Clock Source section of the data sheet 

    Regards,

    Sreenivasa

  • Hi Board designers, 

    MCU_OSC0 receives power from VDDS_OSC (VDDS_OSC0 for AM62L) and the MCU_OSC0_XI input is not fail-safe, so the external 1.8V LVCMOS clock source connected to MCU_OSC0_XI must be the same power source that sources VDDS_OSC (VDDS_OSC0 for AM62L).

    There will not be a power sequencing problem if you connect it as described above.

    Regards,

    Sreenivasa

  • Hi Board designers, 

    Currently the following data sheets have been updated

    AM62Lx Sitara Processors datasheet
    https://www.ti.com/lit/pdf/SPRSPA1

    AM62Dx Sitar Processors datasheet
    www.ti.com/.../sprspb5

    AM62Ax Sitara Processors Data Sheet 
    www.ti.com/.../sprsp77

    AM62Px Sitara Processors datasheet 
    https://www.ti.com/lit/pdf/sprsp89

    Regards,

    Sreenivasa

  • Hi Board designers, 

    Is there LVCMOS clock specs for LFOSC0?

    It is recommended to follow the frequency and PPM requirements specified for the crystal in the below table

    LFOSC0 Crystal Electrical Characteristics

    VDDS_OSC0

    LFOSC0 receives power from VDDS_OSC (VDDS_RTC for AM62L), and the LFOSC0_Xi input is not fail-safe, so the external 1.8V LVCMOS clock source connected to LFOSC0_Xi must be the same power source that sources VDDS_OSC (VDDS_RTC for AM62L).

    regards,

    Sreenivasa

  • Hi Board designers, 

    Connecting LFOSC0 when not used

    Regards,

    Sreenivasa