Tool/software:
Hi TI Experts,
Do you have recommendations on using the IBIS model?
Hi Board Designers,
IBIS model is showing "NC" for MIPI signals.
Below is the model used.
Can u provide an updated model for this Interface with Buffers.
Did you have a chance to check the AMI model?
The link when downloaded is showing .exe file.
Do we need to install the app to access the IBIS-AMI?
Don't we have any readily available IBIS-AMI models for MIPI-CSI 0/1 interfaces. If there is any model available pls do send me.You should be able to double click on the .exe file to install the IBIS-AMI models. This is the only supported option.
Regards,
Sreenivasa
Hi Board Designers,
Inputs related to use case for IBIS and IBIS-AMI simulation models
Four different IBIS and AMI models are provided for AM62Ax.
What are the differences between these models? What is each one used for?
For AM62A, two types of packages, AMB and ANF, are available.
Are the following two models for the ANF package, and the remaining two models for the AMB package?
Is an AMI model for high-speed interfaces?
AMI ModelIs an IBIS model used for LPDDR4?
IBIS-AMI models are used exclusively for simulating high speed (SerDes) interfaces.
For simulating all other interfaces the IBIS model can be used.
Models explicitly specified as ANF are for the ANF package while other models are for the AMB package.
Please note that the recommendation is to use the matching simulation models (for the packages) based on the package selected.
Additional inputs:
IBIS stands for Input/Output Buffering Information Specifications while AMI stands for Algorithm modeling Interface.
In short, IBIS is used to describe analog behavior of the input or output structure of the buffer or device while IBIS-AMI also
discusses high speed signal path behavior. Here are some details about each model:
IBIS-AMI:
1). Typically comes with DLL and s-parameter files to enable a simulation environment where the user can specify ASIC TX, ASIC RX,
and transmission media. Using this environment the user can do signal integrity analyses.
2). S-parameter files can be used to check/study s-parameter behavior across signal frequency of interest.
3). ASIC TX, RX, and device under test jitter dependent behavior signal integrity can be studied and analyzed.
4). Allows ASIC and DUT study of equalization on both transmit and receive sides.
5). Mainly used for giga bit/bits per second high speed signal modeling
6). Figure below shows IBIS-AMI result using BERT, TL1 s-parameter, DS160PR810 EQ boost model, and ouput eye diagram using real time scope and comparing with IBIS-AMI result:
IBIS:
1). Typically it is a single file that allows study of analog buffer on TX and RX sides
2). ESD structure, output/input buffer, and device package lumped behavior is modeled
3). Used for low speed less than giga bits per second analog buffer behavior
4). Mainly used for I vs. V similar to a curve tracer and V vs time
Regards,
Sreenivasa
Hi Board Designers,
Inputs related to IBIS model probe point:
Could you tell us about the probe point when we simulate with IBIS model?
Which edge should customer use Die or Pad when at SoC side/Reads?
(We wonder the the probe point which defined of spec of Reads.)
DDR4/LPDDR4 read simulations must show margin against the provided eye mask at the SoC DiePad. All other measurements are at the DRAM package pin as defined by the JEDEC spec.
DDR4/LPDDR4 uses both rising and falling edges of the DQS strobe during reads.
Refe to AM62x, AM62Lx DDR Board Design and Layout Guidelines www.ti.com/.../sprad06c.pdf
4.5.3.3 Mask Report
The minimum jitter and noise margins are to be captured with respect to the eye masks. This masks are data
rate dependent, and includes:
• Data read eye mask at the SOC die pad for functionality testing.
• Data write eye mask (JEDEC spec) at the DRAM pin/BGA for compliance testing.
• CA bus eye mask (JEDEC spec) at the DRAM pin/BGA for compliance testing.
Table 4-3. LPDDR4 Eye Mask Definitions/Requirements
Read eye masks are defined here.
I was getting eye diagrams that look like the image pasted below. I have since found that it is a lot cleaner when using the die-side probing option in my simulation software. Models from the last interface I simulated did not have a built in package model, so I wasn't aware you could do that.
It makes sense that die side probing would be what we'd ultimately care about. Let me know if that is not how it is intended to be used though.
There is no generic guideline that can be given. Different simulations require different points at which the signal needs to be probed and also with different specifications.
For e.g. the DDR JEDEC specifications for Write transactions require waveforms to be measured at the DRAM BGA, whereas the Read transactions require waveforms to be measured at the SoC Die.
Regards,
Sreenivasa
