[FAQ] AM625 / AM623 / AM620-Q1 / AM62Ax / AM62Px / AM62D-Q1 / AM62L / AM64x / AM243x Design Recommendations / Custom board hardware design - Queries related to IBIS model

Hi Board Designers, 

Refer below input.

Q1. Is there a limitation on the number of devices that could be connected to emulated I2C interface given these are LVCMOS IO buffers compared to the Open drain type I2C interface.

We have customer reusing the current measurement part of the SK 6 INAs, plus 1..2 X EEPROMs + 2 X temp sensors being connected to the emulated I2C interface.

Answer: The low-level output current (IOL) and output low voltage (VOL) parameters are different for the two ports.  I would not expect any significant functional difference between the these ports with one or two loads.  However, they may observe bigger differences as the number of loads increase.  I’m not able to say how many loads can be connected before it becomes problematic because this depends on the attached devices and the PCB layout.  I recommend they perform a signal quality simulation using the IBIS models of each device along with their actual PCB extractions to confirm the signal levels and signal settling time does not violate any of the I2C specifications.

Q2. LVCMOS output pin with 1.8VMODE

The output buffer will source current from the respective VDD IO power rail to the external connections when driven high,
or sink current from the external connections to VSS when driven low. The signal voltage will depend on the source current or sink current.
The only data point we define in the datasheet is for current up to 3mA, where the signal voltage will remain less than the max VOL value of 0.45V as
long as the sink current is less than 3mA, and the signal voltage will remain greater than the min VOH value of (VDD - 0.45V) as long as the source
current is less than 3mA. The internal voltage dropped across the output buffer will decrease as the current decreases.
A typical LVCMOS input buffer only has a few uA of input leakage current that needs to be driven by the output buffer to hold a valid logic state.
There is a good chance external pulls, internal pulls, or combinations of external and internal pulls will present a much larger load than all attached
input buffers.
We provide an IBIS model of the output buffer that can be used to determine the resulting signal voltage for operating conditions not defined in the
datasheet. You will need to create a simulation environment that represents your specific implementation and use the IBIS files of each device to
determine the steady-state signal voltage for your specific system implementation if you are connecting a device that requires a logic high signal
voltage that is greater than the min VOH value of (VDD - 0.45V) or a logic low signal voltage that is less than the max VOL value of 0.45V.

Regards,

Sreenivasa 

Hi Board Designers, 

Refer below FAQs

(+) [FAQ] Using DDR IBIS Models for AM64x, AM62x, AM62Ax, AM62Px - Processors forum - Processors - TI E2E support forums

Regards,

Sreenivasa