Hi Board designers,
The FAQ is generic and can also be used for
AM64x
AM243x (ALV, ALX)
Refer below inputs:
External LVCMOS clock specifications:
Customer needs to confirm the TI clock source they select meets the requirements as per the AM64x datasheet.
The non-SerDes use case requirements have already been added to the datasheets of several newer devices. You can reference the AM62Ax, AM62Dx, or AM62Px datasheets to see these requirements, which are the same as the AM64x non-SerDes use case requirements.
The AM64x datasheet will have an additional Phase Noise parameter that must be applied if they are planning to use the AM64x SerDes to implement USB SuperSpeed or PCIe operating without a common external clock source.
The Phase Noise parameter is only applicable when the SerDes PHY is used for USB SuperSpeed, or PCIe operating without a common external clock source.
Connection of LVCMOS clock input
1.8V LVCMOS-Compatible Clock Input
The clock inputs are not fail-safe
The clock inputs are referenced to 1.8V, VDDS_OSC0.
The Clock input is not fail-safe
It is recommended to connect the Oscillator supply to the same supply that is connected to the VDDS_OSC0
Is there any concerns using LVCMOS clock input
Using a crystal to create a reference clock for AM62x family of processors is preferred because there is less risk of clock jitter issues.
There is no concern using LVCMOS clock input. Follow the above specifications while selecting the oscillator. If you use a LVCMOS oscillator, select one that doesn't contain a PLL. LVCMOS clock sources that only implement a crystal oscillator operating in fundamental oscillation mode provides lower clock jitter than one with a PLL.
Ensure you follow the Note added in the MCU_OSC0 LVCMOS Digital Clock Source section of the data sheet
There is the description “A DC steady-state condition is not allowed on MCU_OSC0_XI when the oscillator is powered up.” at 6.10.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source in the datasheet.
Why is inversion logic necessary?
The inverter shown in the diagram was meant to represent an LVCMOS output, where the LVCMOS output could be the oscillator output buffer, or the LVCMOS output from some clock distribution device. There is no requirement to invert the clock source.
Is it no problem that LMK1C1104 and LMK6CE02500 are directly connected to MCU_OSC0_XI like below ? or Should C-cut (C coupling) be needed ?
You should connect the 1.8V LVCMOS clock source output directly to the XI pin and connect the XO pin to VSS.
There are internal AC coupling capacitors in both of the XI and XO signal paths that connect to an internal comparator that creates a square wave from the crystal circuit oscillation. A DC steady-state condition on the XI pin relative to the XO pin would allow the comparator to generate glitches on the internal clock tree of the device and cause it to do unpredictable things.
Regards,
Sreenivasa
