• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Subscribers 98 subscribers
  • Views 353 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM62L: AM62L3 NAND Boot from redundant address

Fabian Godehardt
Prodigy 60 points

Part Number: AM62L

Hi,

TRM says in chapter "Two Stage Boot Behaviour" that if tiboot3.bin fails to boot from Main address it will boot from the redundant address. This will apply for Stage 1 and Stage2 images.
Stage2 will use redundant address if Stage1 is also booted from redundant address.

According do DTS in the SDK I setup the NAND partitions with tiboot3.bin and tispl.bin at the main and backup locations in NAND flash:


                       partition@0 {
                               label = "NAND.tiboot3";
                               reg = <0x00000000 0x00080000>;  /* 512KB */
                       };
                       partition@80000 {
                               label = "NAND.tispl";
                               reg = <0x80000 0x180000>; /* 1.5M */
                       };
                       partition@200000 {
                               label = "NAND.u-boot";
                               reg = <0x00200000 0x00200000>;  /* 2M */
                       };
                       partition@400000 {
                               label = "NAND.tiboot3.backup";  /* 512KB */
                               reg = <0x00400000 0x00080000>;  /* BootROM looks at 4M */
                       };
                       partition@480000 {
                               label = "NAND.tispl.bin.backup";
                               reg = <0x00480000 0x180000>; /* 1.5M */
                       };

Then I setup boot pins (only reduced mode is available on our board) to use EFUSE1 boot mode, right after fuses where set to use GPMC NAND as primary and UART as secondary bootmode.

This works fine with images located on the main adresses in NAND flash.

Then I deleted the tiboot3.bin and tispl.bin in the main areas on NAND flash.

This fails. The tiboot3.bin from backup area seems to start (bl1 prints some messages) but starting the tispl.bin from backup area seems to fail. AFAICS Errata does not mention there is a problem with this setup.

Erasing tiboot3.bin in main area and tispl.bin in backup ares (so keep tispl.bin in the main area/partition intact) also boots. But this differs from described behaviour in the TRM and a backup of tispl.bin makes no sense here.

Question is: What must be setup to boot both, tiboot3.bin and tispl.bin, from the backup areas?

Thanks in advance!

Fabian

  • 0
    TI__Guru* 77840 points

    Hi Fabian,
    Let me test it on my setup, and will get back to you next week.
    Best,
    -Hong

  • 0 in reply to Hong Guan64
    Prodigy 60 points

    Hi Hong,

    thanks for your support. In this context, could you please also clarify whether there is a register that reflects the main or backup boot in stages after tispl.bin was started? We will may use identical images for both slots, so it would be good to detect problems with early loaders on later stages for example on an update process.
    Thanks in advance!

    Fabian

  • +1 in reply to Fabian Godehardt
    TI__Guru* 77840 points

    Hi Fabian,
    Can we try the attached BL1 patch on your setup?
    Best,
    -Hong

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/0001_2D00_Add_2D00_BL1_2D00_support_2D00_on_2D00_passing_2D00_the_2D00_tispl.bin_2D00_offset_2D00_to_2D00_R.patch

  • 0 in reply to Hong Guan64
    Prodigy 60 points

    Hi Hong,

    thanks for your support! That does the trick :) and GPMC NAND backup boot works now.
    Boot with tiboot3.bin and tispl.bin in main stages:


    NOTICE:   ROM_TABLE_PERIPHERAL =0x8c 
    NOTICE:   ROM_TABLE_GPMC_READINDEX =0x0

    Boot from backup stages:

    NOTICE: ROM_TABLE_PERIPHERAL =0x8c
    NOTICE: ROM_TABLE_GPMC_READINDEX =0x1

    As ROM_TABLE_GPMC_READINDEX lies within the MSRAM_96K0_RAM space, will this be a fixed address even across possible future ROM versions of newer CPU revisions? So can we directly use it for our backup boot detection / update handling?
    Thanks in advance!

    Fabian

  • 0 in reply to Fabian Godehardt
    TI__Guru* 77840 points

    Hi Fabian,

    Thanks for your confirmation the patch worked on booting tiboot3.bin/tisp.bin from either primary or redundant GPMC-NAND partition on your setup.

    As you know, once the 1st stage BL (tiboot3.bin) boots after authenticated and loaded by ROM, the 1st stage BL needs to provide the 2nd stage BL information (i.e. file name or offset... depending on the boot media) to ROM in order for ROM to load the 2nd stage BL.

    Please refer to <5.7 Boot Parameter Tables> in AM62L TRM for the information on the Boot Peripheral, Read Index etc... and <5.9.1 Global Memory Addresses Used by ROM Code> lists the ROM boot parameter entry. In case of future Silicon Revision (SR), the ROM boot parameter table entry is patchable in the 1st stage BL (TF-A) by detecting the SR via reading the MMR register.

    Best,
    -Hong

  • 0 in reply to Hong Guan64
    Prodigy 60 points

    Hi Hong,

    understood. Thanks for your support!

    Fabian