Texas Instruments (TI) Processors support forum is an extensive online knowledge base where millions of technical questions and solutions are available 24/7. You can search processors content or ask technical support questions on Sitara™ processors, digital signal processors (DSP) and automotive processors. Find the right solution for your circuit design challenges by using our TI E2E™ support forums that are supported by thousands of contributing TI experts.
Frequent questions

  • [FAQ] AM625: OSPI Access Across Different Cores

    Part Number: AM625 Other Parts Discussed in Thread: AM62P , AM62L On different TI SITARA MPU SoCs, lets have a look at SoC wise cores which have access to the OSPI module/Controller in the current MCU+ SDK Software offering. Please refer the table below…

  • [FAQ] AM625: How to configure Timer in Interrupt mode

    Part Number: AM625 Other Parts Discussed in Thread: SYSCONFIG Lets have a look at the implementation of application using a TIMER module(DM TIMER) in Interupt mode of operation. The application code can be used as it is or as a baseline for configuring…

  • [FAQ] AM62D-Q1 Custom board hardware design – AUDIO-AM62D-EVM Audio Functionality Implementation Related Queries and Design Notes

    Part Number: AM62D-Q1 Other Parts Discussed in Thread: AUDIO-AM62D-EVM Hi TI experts, I am planning to reuse the AM62D-Q1 AUDIO-AM62D-EVM schematics for my custom board design. I see the below schematic sections (pages) added to the AUDIO-AM62D-EVM…

  • [FAQ] AM6421: RESETSTATz output during ROM boot

    Part Number: AM6421 Hello, During a successful QSPI boot, I have captured the following signals: MCU_PORz, RESETSTATz, OSPI_CLK, OSPI_CS. I'm observing that roughly 35mS after RESETSTATz goe high it has a 160uS period where it drops low. Looking at…

  • [FAQ] TDA4VH-Q1: How to configure the SerDes lane for PCIe, USB, Ethernet, and Display in Linux?

    Part Number: TDA4VH-Q1 Other Parts Discussed in Thread: TDA4VH The high speed interfaces on the TDA4x share the SerDes lanes. The lanes can be muxed for different interfaces, but how can I configure them within Linux?

  • [FAQ] AM2754-Q1: Working Configurations for 8S-8S-8S on S28HS512T Serial NOR OSPI Flash

    Part Number: AM2754-Q1 Other Parts Discussed in Thread: SYSCONFIG In MCU+ SDK 11.02, the OSPI and Flash examples are configured by default to operate at the highest protocol: 8D-8D-8D. For configuring 8S-8S-8S SDR Protocol on S28HS512T Serial NOR OSPI…

  • [FAQ] TDA4VH-Q1,TDA4VE,TDAVAL,TDA4VL,TDA4VP-Q1,TDA4AP-Q1: How to reset C7x and load binary faster via CCS

    Part Number: TDA4VH-Q1 Hi, After reset of C7x, i am trying to load newer C7x binary, but the second load takes a lot of time. Could you please help me to solve this issue.

  • [FAQ] AM64/AM243: Facing an issue with CCS when trying to flash an image using SBL JTAG UNIFLASH

    Part Number: AM6442 Other Parts Discussed in Thread: UNIFLASH I am trying to flash an image for AM64/AM243 device by loading SBL JTAG UNIFLASH from CCS version 20. *.* , after following the steps mentioned in the MCU+SDK documentation: https://software…

  • [FAQ] AM62A7-Q1: How to reset C7x core via CCS?

    Part Number: AM62A7-Q1 Hi, I am trying to do CPU reset for C7x core on AM62Ax device and facing a page fault error. Below is the error message. "(Error -1351 - (0:0:0)) Register or Memory request has timed out. The CPU is executing a High Priority…

  • [FAQ] AM62D-Q1: Understanding MCASP Audio Pipeline Latency(MCU PLUS SDK) - Buffer Priming and Pipeline Delays

    Part Number: AM62D-Q1 When implementing audio input/output systems using MCASP (Multichannel Audio Serial Port), there is inherent latency in the audio pipeline(SW) due to buffer priming and the DMA queuing mechanism. This FAQ explains the fundamental…

View FAQ threads