TDA4VM: TDA4VM - How to config RAT on R5F core

billy he

Part Number: TDA4VM

Hi expert.

We haved found PDK PCIe drv haved provide example code run on R5F,The example code can work normally on PCIe0 and PCIe1 controller。However,when we try to using the example code on PCIe 2 controller,it can't work.Because the address of the PCIe 2 controller "cfg" register is at 0x4400000000。normally ,R5F can't access address longer than 32bit. We found R5F can use RAT( Region-based Address Translation) to access address 32bit - 48bit, but we only can find RAT config code on c66 core.

Our questios is ：How do we use RTA on R5F, do you have example code for configuring R5F RAT, if you have, please provide us。

another question：Have you used pcie2 control in the PDK code? Can we use pcie2 directly with the PDK PCIe drv example code?

pcie2_rc: pcie@2920000 {
       compatible = "ti,j721e-pcie-host";
       reg = <0x00 0x02920000 0x00 0x1000>,
              <0x00 0x02927000 0x00 0x400>,
              <0x00 0x0e000000 0x00 0x00800000>,
              <0x44 0x00000000 0x00 0x00001000>;
       reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
       ti,syscon-pcie-ctrl = <&pcie2_ctrl>;
       max-link-speed = <3>;
       num-lanes = <2>;

..............

thank

over 4 years ago

+1 Karan Saxena over 4 years ago

TI__Guru* 77904 points

Hi,

On the RAT configuration please refer to the below code snippets. I have added an assembly version, GEL file version as well as a c code version.

Please note that the RAT module is different for different R5F cores, so you need to do the RAT configuration from the same core.

Note the base address of RAT for MCU R5 and MAIN R5s are different. 0x40F90000 vs 0x0FF90000.

Can you please create another thread for the PCIe question? We will ask our PCIe expert to address that. On this thread we can continue if you see issues with RAT config.

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;
;
; ======== ratConf.asm ========
; Sets the RAT for the main domain to map 40-bit ocmram address to 32-bit space
;
    .text
    .sect   ".ratConf"
;==============================================================================
;   void ratConf( void )
;==============================================================================
    .global ti_sysbios_family_arm_v7r_keystone3_Hwi_vectors

    .global ratConf

ratConf:
        .asmfunc
        push.w  {r0, r1, r5, r7}
        movw    r0, #0x0040
        movt    r0, #0x0FF9
        movw    r1, #0x0013
        movt    r1, #0x8000
        str     r1, [r0]

        movw    r1, #0x0000
        movt    r1, #0xD000
        str     r1, [r0, #0x4]

        movw    r1, #0x0000
        movt    r1, #0x0200
        str     r1, [r0, #0x8]

        movw    r1, #0x004F
        movt    r1, #0x0000
        str     r1, [r0, #0xc]
        pop.w   {r0, r1, r5, r7}

        beq     exit
exit:
        bx      lr
        .endasmfunc

        .end

Equivalent GEL code is:

hotmenu Configure_RAT_50000000(){
        // region 1
                GEL_TextOut( "Mapping MAIN OCM @ 0x4F_0200_0000 to 0xD000_0000\n");
        *(unsigned int *)(0x0FF90000 + 0x44) = 0xD0000000;  //IN ADDRESS
        *(unsigned int *)(0x0FF90000 + 0x48) = 0x02000000;  //OUT ADDRESS
        *(unsigned int *)(0x0FF90000 + 0x4C) = 0x0000004F;  //Upper 16 bits of the real physical address.
        *(unsigned int *)(0x0FF90000 + 0x40) = 0x80000013;
}

c code for this:

/* Check this header file for more info */
#include <ti/csl/csl_rat.h>
...
...
...
#if defined(SOC_J721E) && defined(MCU1_0)
#define RAT_CFG_BASE_ADDR CSL_MCU_ARMSS_RAT_CFG_BASE
#if defined(SOC_J721E) && defined(MCU2_0)
#define RAT_CFG_BASE_ADDR CSL_ARMSS_RAT_CFG_BASE
#endif
...
...
...
void ratConf(void)
{
    CSL_RatTranslationCfgInfo translationCfg;
	
	/* Add RAT configuration to access address > 32bit address range */
	
	/* Translated address returned on a successful match */
	translationCfg.translatedAddress    = ADDR_GREATER_THAN_32_BIT;
	/* Size of region in Bytes */
	translationCfg.sizeInBytes          = SIZE_IN_BYTES;
	/* 32-bit base address used in the address comparison */
	translationCfg.baseAddress          = ADDR_32_BIT;

	/* Set up RAT translation */
	bool result = CSL_ratConfigRegionTranslation((CSL_ratRegs *)RAT_CFG_BASE_ADDR,
												0U,
												&translationCfg);
	if (result == false)
	{
		sbl_puts("App: CSL_ratConfigRegionTranslation Failed! \n");
	}
	else
	{
		sbl_puts("App: CSL_ratConfigRegionTranslation Successful! \n");
	}
}

Regards,

Karan

0 billy he over 4 years ago

Prodigy 230 points

hi Karan Saxena：

I used the GEL code, and MAIN R5s RTA works well. but I am still confused about the parameter "IN ADDRESS". It works well when using D0000000 or 0x80000000, but it does not work when using 0x10000000, it will stuck when configuring RAT. Are there any requirements for the parameter "IN ADDRESS"?

thanks.

+1 Karan Saxena over 4 years ago

TI__Guru* 77904 points

Hi,

That could be because you need to have the R5F MPU setup to access the IN ADDRESS. So if you want to access address 0x4F_0200_0000 and you map it to some 32 bit address - then that 32 bit address needs to be accessible from the R5F.

In your case your MPU should have a valid entry for 0x1000_0000.

Regards,

Karan

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TDA4VM: TDA4VM - How to config RAT on R5F core