Part Number: PROCESSOR-SDK-J721E
Other Parts Discussed in Thread: TDA4VM
Hi Team,
In our custom board we have the Serdes muxing as below:
Serdes 0 : lane 0 -> SGMII
Serdes 0 : lane 1 -> SGMII
Serdes 1 : lane 1 -> SGMII
Serdes 3 : USB3 (Type C)
Referring to the k3-j721e-r5-common-proc-board.dts -> serdes_wiz0: wiz@5000000
As per DT bindings for this node, there should be a "Serdes" sub-node and in evm it is pointing to PCIe link @ serdes0 with (PHY_TYPE_PCIE).
serdes0: serdes@5000000 {
compatible = "cdns,ti,sierra-phy-t0";
reg-names = "serdes";
reg = <0x00 0x5000000 0x00 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&serdes_wiz0 0>;
reset-names = "sierra_reset";
clocks = <&wiz0_cmn_refclk>, <&wiz0_cmn_refclk1>;
clock-names = "cmn_refclk", "cmn_refclk1";
u-boot,dm-spl;
}
&serdes0 {
serdes0_pcie_link: link@0 {
reg = <0>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz0 1>;
u-boot,dm-spl;
};
};
For my custom board case, how this node should be ?