AM1808 DDR2 memory routing

Christian Riesch

Other Parts Discussed in Thread: AM1808

Hi,

In the AM1808 data sheet, section 6.11.3.11, the requirement no. 1 "Center to Center CK-CKN Spacing" is given as max. 2w, where w is w = PCB trace width as defined in Table 6-27. Note 2 adds that "Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion.".

So my question is: If center to center spacing may fall down to w, and w is the width of both traces, wouldn't that result in a short circuit?

Could you please help me to understand these specifications?

Regards, Christian

over 14 years ago

0 jc-ti over 14 years ago

TI__Mastermind 27585 points

Thats correct. It is a typo and meant that the spacing itself may fall to w, which gives a center-to-center spacing of 2w. We will correct the documentation.

Jeff

0 Christian Riesch over 14 years ago in reply to jc-ti

Intellectual 710 points

Hi Jeff,

Thank you for your response. How about the "Center to Center CK-CKN Spacing" In Table 6-34? It is given as 2w maximum, together with the information from your response (2w minimum) this would require that spacing must always be w and center-to-center spacing 2w.

Christian

0 jc-ti over 14 years ago in reply to Christian Riesch

TI__Mastermind 27585 points

Yes that is correct.

Jeff

0 RY9983 over 13 years ago in reply to jc-ti

Guru 10570 points

Hello, Jeff.

So, I think that the note has no meaning from your answer.
Bacause..
- Center to Center CK-CKN Spacing .. 2w[MAX]
- It is meant that the spacing itself may fall to w, which gives a center-to-center spacing of 2w. (from your answer)

Right?

And, How about the "Center to center DQS to other DDR2/mDDR trace spacing"?
The datasheet describes:
- Center to center DQS to other DDR2/mDDR trace spacing .. 4w[MIN]
- Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion.

Thank you for helping me.

Best regards,
RY

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AM1808 DDR2 memory routing