[FAQ] TDA4VM: Documentation for Exception/Trap details

Hi Santosh,

-- 1 --

Illegal operations and traps, are covered in exception handling of ARM Documentation. The exception handling will be specific to the OS in use and the configuration of the ARM registers. 

For example documentation on ARM exceptions for A72 can be found at below links.

• A72 TRM: https://developer.arm.com/documentation/100095/0003 
• https://developer.arm.com/documentation/100095/0002/programmers-model/armv8-a-architecture-concepts/exception-levels
• https://developer.arm.com/documentation/102412/0100/Privilege-and-Exception-levels
• https://developer.arm.com/documentation/102412/0100/Handling-exceptions
• https://developer.arm.com/documentation/102412/0100/Related-information

Please reference Safety Manual, Section 5.1 ARM Cortex-A72 Subsystem, subsection Guidelines on Diagnostic Implementation, 2nd paragraph for a write up on this

Links for R5 TRM and exception section are below.

• Cortex-R5 - ARM
• Cortex-R5 Technical Reference Manual r1p2 (arm.com)

-- 2 --

No.  Not all exceptions will directly trigger the ESM interrupt. The exception handler would need to signal the ESM or use alternative mechanism to indicate to external system that an error has occurred.

-- 3--

SDK exception handling is dependent on the HLOS in use, for Linux / QNX information would be available online.

The SDL (Software Diagnostics Library) does provide examples of exception handlers. 

If further detail on 1,2,3 is desired, please use the private forum, or reach out to your local TI contact.

Regards,

kb